Philippe Gastaldo Photo_UnitySC_Product and R&D Director
Philippe Gastaldo Photo_UnitySC_Product and R&D Director
Philippe Gastaldo Photo_UnitySC_Product and R&D Director
Philippe Gastaldo Photo_UnitySC_Product and R&D Director
Philippe Gastaldo Photo_UnitySC_Product and R&D Director

Overcoming thin-wafer inspection challenges for high-volume manufacturing

Aug. 23, 2017

As the automotive electronics market continues to grow, spurred by developments such as semi-autonomous and fully autonomous vehicles, the demand is increasing for power semiconductor components with sophisticated conversion schemes that decrease power consumption and heat. To address these needs, power semiconductor manufacturers are turning to thin wafers.

Today’s power semiconductors are manufactured primarily on 200-mm wafers that range in thickness from 50 to 100 µm, but their roadmaps are targeting wafers as thin as 1 µm. These wafers are thinned on the backside by mechanical polishing. Defects resulting from the polishing process include grinding marks, grinding failures resulting in edge chips, star cracks and comets formed by edge particles that get caught in the grinding wheel, embedded particles, cleavage lines, and a variety of other imperfections.

Because these defects often appear on the wafer backside rather than the active side, they are not as much of an issue for thicker wafers. But as wafers become increasingly thinner, these defects are affecting chip reliability. While the backside defects in thinned wafers don’t initially impede the chip’s functionality, they do impact the device’s overall reliability. In fact, a power semiconductor can easily be processed through to final packaging without detecting the defects. However, when subjected to the high temperatures of an automotive application, for example, a crack can form and lead to chip failure.

While thin-wafer inspection has become critically important for the wafer-sorting process, as well as helping engineers improve thinning processes themselves, many of the existing technologies are limited and inadequate for detecting defects.

Most of today’s defect inspection is done manually, by visual inspection, using a powerful light, but without magnification. As this process is often performed by different operators, it’s not repeatable and results in minimal defect information that lacks accurate classification.

Automated optical inspection that uses a camera with magnification has also been tried, without success, because while it provides an automated and repeatable process, it is not capable of inspecting the wafer topography to distinguish between grinding marks and deep cracks.

Some have considered darkfield inspection an option for detecting defects in thin wafers. Based on optical technology, darkfield is the measurement of light reflected at a lower angle. While darkfield is useful for front-end inspection, backside grinding renders it ineffective due to the resulting wafer-surface roughness. As a result, darkfield inspection should be avoided following backside grinding.

Optimal thin-wafer inspection requires a technology that is sensitive to nanotopography and that can both detect and measure surface variations of nanometric proportions. Interferometry, a measurement method using the phenomenon of interference of light, radio or sound waves,1 is capable of this, but many tools based on interferometry are slow and expensive with low throughput. Additionally, while interferometry is an excellent option for some surface-inspection applications, it is not suitable for inspecting and sorting thin wafers in a high-volume manufacturing environment.

Alternatively, there is a technology known as phase-shift deflectometry (PSD) that measures the wafer-surface topography by imaging through the surface and generating a pattern on the tool display. Topography variation on the surface changes the shape of the pattern, which indicates the presence of a defect. By generating images of the topography map, pitch analysis can be performed to accurately classify the defect while providing its size and depth. Used until recently for silicon-on-insulator (SoI) and epitaxial (EPI) wafer inspection and slip-line detection, PSD is gaining traction for wafer-thinning inspection.

Companies that work with ultra-thin wafers are beginning to employ PSD technology that is both cost-effective and fast enough for high-volume manufacturing. Additionally, some companies are beginning to integrate automatic classification software that provides accurate and detailed defect information. This approach, with its advantages over the predominant visual inspection currently being employed by most manufacturers, is expected to become the preferred method for thin-wafer inspection—particularly in power semiconductor applications for mission-critical applications like automotive.

Reference

  1. Interferometry Explained,” How does it work? Renishaw plc.

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