Fort Worth, TX. Synopsys Inc. at the International Test Conference made news on several fronts. The company introduced a validated built-in-self-test (BIST) and repair IP solution to enable designers to achieve stringent levels of functional safety for automotive system-on-chips (SoCs).
Synopsys also said that SGS-TÜV Saar GmbH has certified several of its tools for the ISO 26262 automotive functional safety standard, that DecaWave had deployed TetraMAX II ATPG to reduce runtime, and that a new suite of embedded memory test and repair features for its DesignWare STAR Memory System solution would enable increased test coverage and faster power-on initialization for automotive, mobile, and cloud-computing SoCs.
The BIST and repair IP solution for automotive SoCs includes the ASIL D Ready Certified DesignWare STAR Memory System, STAR Hierarchical System, and DFTMAX LogicBIST software qualification kit, as well as ARC HS processors, providing test and repair of memory and logic blocks with automatic test integration and validation of analog/mixed-signal IP. By providing a preverified functional safety test solution, Synopsys said it is helping designers ensure high test coverage, achieve low defective parts per million (DPPM), and reach the required automotive safety integrity levels (ASILs) of their automotive designs.
“Safety-critical automotive SoCs need to control run-time scheduling, manage switching activity, and monitor the status of the logic and memory BIST,” said Christophe Eychenne, DFT architect at Bosch, in a press release. “Synopsys’s ASIL D Ready Certified functional safety test solutions can fully support our requirements for high detection of logic and memory faults, self-test power up, and mission-mode testing of our ADAS SoCs.”
At the 2nd IEEE International Workshop on Automotive Reliability & Test (ART17), held in conjunction with ITC, Eychenne presented a paper titled “System-on-Chip Online Self-Test Runtime Control for Functional Safety,” which he coauthored along with G. Harutyunyan and Y. Zorian of Synopsys. In his presentation, Eychenne described requirements for in-field testing of vehicle ICs at power-up and on-the-fly, and he elaborated on the use of the STAR Hierarchical System and DFTMAX LogicBIST for such applications.
Synopsys also announced that its test platform tools for high-quality manufacturing test are certified for the ISO 26262 automotive functional safety standard. To achieve this, SGS-TÜV Saar GmbH, an independent accredited assessor, recently certified the tool qualification reports for the DFTMAX, DFTMAX Ultra, and DFTMAX LogicBIST solutions. These certifications are in addition to previously certified Synopsys test products that include TetraMAX II ATPG solution, DesignWare STAR Memory System, and STAR Hierarchical System. Certification provides designers the confidence in the use of the Synopsys test solution for safety-critical automotive applications and accelerates functional safety qualification for automotive ICs, up to the requirements for ASIL D.
“Reducing risk is critical to ensure functional safety for automotive electronic systems, such as advanced driver-assistance systems,” said Gudrun Neumann, head of functional safety software at SGS Group, SGS-TÜV Saar GmbH, in a press release. “For safety-critical automotive applications, designer confidence in tools and IP rises when they satisfy the qualification requirements of the ISO 26262 automotive functional safety standard. We issued certificates to Synopsys test platform tools and tool qualification reports based on a successful evaluation against the requirements of ISO 26262.”
Synopsys also announced that DecaWave, a manufacturer of low-cost, low-power indoor positioning ICs and modules, deployed TetraMAX II ATPG to reduce runtime from nine hours to thirty minutes and reduce the number of patterns by 50% compared to its previous test-pattern generation solution for an automotive ultrawide band transceiver IC. The lower pattern count enabled DecaWave to meet the challenge of high-quality manufacturing testing within a limited amount of tester time. DecaWave incorporated the TetraMAX II solution into its flow with minimal effort and produced improved results within an hour. As a result of this success, DecaWave is standardizing on Synopsys’ TetraMAX II solution for all future designs to minimize silicon test costs and maximize test quality.
And finally, Synopsys announced a new suite of embedded memory test and repair features for its DesignWare STAR Memory System solution to enable increased test coverage and faster power-on initialization for high-performance automotive, mobile, and cloud computing SoCs. With these new features, designers can achieve a 10x reduction in repair time by eliminating extra cycles and testing only faulty memories. The STAR Memory System includes enhanced hardware and test algorithms to detect and correct a wide variety of dynamic faults prevalent in advanced process technologies, including 7-nm FinFET, both in production test and in the field. In addition, its EC) compiler mitigates the impact of soft errors by calculating the memory failures in time (FIT) rate, enabling designers to improve the reliability of their systems.
“Moving to a new process node, especially in small geometries, is a big challenge,” said Spark Zhang, DFT engineer at HiSilicon, I a press release. “Using the DesignWare STAR Memory System helped us meet our power, performance, area, and test targets, resulting in first-pass silicon success for our 7-nm FinFET SoC.”