The International Test Conference was held Oct. 29-Nov. 3, 2017, in Fort Worth, TX. The week included three days of exhibits and technical presentations bracketed by tutorials and workshops. A key emphasis was on automotive, followed by data analytics.
Board- and system-level test was the focus of a Monday tutorial. Krishnendu (Krish) Chakrabarty described board- and system-level test challenges and why chips that pass ATE test can fail in boards and systems, and it proposed machine-learning techniques to address the challenges.
Robert Klosterboer, executive vice president and general manager of the Analog Solutions Group at ON Semiconductor, delivered a Tuesday keynote address in which he discussed “testing beyond the green light.” The pass/fail results of previous days have given way to a test environment driven by machine learning and artificial intelligence, he said. Data gathering is key, Klosterboer added, often assisted by DFT.
Optimal+ hosted a luncheon session Tuesday at which CTO Michael Schuldenfrei outlined the company’s approach to machine learning as applied to semiconductor test. He described a machine-learning project as having four distinct states: learn (use historical data to build and test a model), act (deploy the model to do something), validate (measure the model’s performance as things change), and adapt (refresh the model as it degrades, and improve the algorithms).
He said companies face several challenges: they lack the time and resources to address machine learning, their data scientists are backlogged, or the data scientists have developed great algorithms but can’t replicate early successes. The key to success, he said, lies in the infrastructure—not the algorithms. His company’s approach is built on what it calls a global data highway that collects data and runs analytics in real time.
Machine learning is much more than a buzzword, he said, and has many applications to semiconductor manufacturing test. But, he concluded, it’s all about infrastructure. Great algorithms won’t help if you can’t deploy them.
The Wednesday keynote by Sanu Mathew, senior principal engineer, Circuits Research Labs, Intel, discussed security for ultralow-energy IoT devices. The Thursday keynote was delivered by Joachim Kunkel, general manager, Solutions Group, Synopsys. The title was “Look mom! No hands!” He cited IC Insights estimates that the automotive semiconductor market will grow from $25 billion in 2017 to $32 billion by 2020.
System-level test
System-level test was the topic of an ITC virtual panel moderated by test consultant Paul Berndt. The virtual nature of the panel converted the audience into panelists, who could respond online to polling questions and provide Twitter-like 140-character comments. Berndt got the session started by explaining that SLT adds to your test flow one more test step after final package test—one that comes as close as possible to representing your application—somewhat like using an actual cellphone as your testbed for testing a cellphone chip, for example.
In related news, Astronics Test Systems highlighted the expansion of its ATS 5034 system-level-test (SLT) platform. Featuring new semi-automatic solutions in a scalable system, the ATS 5034 now offers lower volume, higher mix, small lot, and/or longer test-duration options for semiconductor manufacturers.
Mentor at ITC highlighted its new Tessent MissionMode product (Figure 1), which combines automation and on-chip IP to test and diagnose automotive semiconductors at any point during a vehicle’s functional operation. Tessent MissionMode integrates the infrastructure for system-software-based access to any test and diagnosis capabilities integrated within an automotive chip. That infrastructure includes an in-system test (IST) controller that drives an internal IEEE 1687 (IJTAG) access network to communicate to any IJTAG-compliant IP. In particular, the IST controller fully supports all Tessent design-for-test products including memory BIST, logic BIST, and EDT logic. The IST controller also provides a communication path to outside the chip through a generic CPU interface. This interface can be adapted to work with any CPU bus protocol typically used in automotive systems—such as Ethernet, CAN, or I2C. The controller also supports direct memory access to test instructions stored in an optional on-chip ROM.
Courtesy of Mentor Graphics
Mentor also highlighted its new VersaPoint test-point technology in its Tessent ScanPro and Tessent LogicBIST products, which maintain ISO 26262 qualification. The VersaPoint test-point technology reduces manufacturing test cost and improves quality of in-system test. Mentor also announced that Renesas Electronics has adopted the VersaPoint technology for its automotive ICs to address safety-critical test requirements to reach Automotive Safety Integrity Level (ASIL) C and D certification.
Synopsys made news on several fronts. The company introduced a validated built-in-self-test (BIST) and repair IP solution to enable designers to achieve stringent levels of functional safety for automotive SoCs. The BIST and repair IP solution for automotive SoCs includes the ASIL D Ready Certified DesignWare STAR Memory System, STAR Hierarchical System, and DFTMAX LogicBIST software qualification kit, as well as ARC HS processors, providing test and repair of memory and logic blocks with automatic test integration and validation of analog/mixed-signal IP. By providing a preverified functional safety test solution, Synopsys said it is helping designers ensure high test coverage, achieve low defective parts per million (DPPM), and reach the required automotive safety integrity levels of their automotive designs.
Synopsys also said that SGS-TÜV Saar GmbH has certified several of its tools for the ISO 26262 automotive functional safety standard, that DecaWave had deployed TetraMAX II ATPG to reduce runtime, and that a new suite of embedded memory test and repair features for its DesignWare STAR Memory System solution would enable increased test coverage and faster power-on initialization for automotive, mobile, and cloud-computing SoCs.
On the exhibit floor, Alliance ATE Consulting Group Inc. announced that Inphi has signed a multiyear Velocity CAE tool licensing agreement, continuing Inphi’s design-to-test partnership with Alliance ATE. GÖPEL electronic, one of the few board-level-test exhibitors, highlighted JTAG-based embedded test. Chroma highlighted its PXI systems for testing IoT and Industry 4.0 ICs. And Roos Instruments highlighted a test system and fixture for 5G ICs.
Advantest demonstrated its Cloud Testing Service, in which test programs reside in the cloud; customers receive a desktop-sized system that’s free with a cloud software subscription. Cadence highlighted its Modus DFT software solution, which supersedes the Encounter Test line that Cadence had acquired from IBM.
Also on the exhibit floor, Aries Electronics and Ironwood Electronics demonstrated test sockets. Aehr Test Systems and Micro Control Co. highlighted burn-in-and-test systems. Marvin Test Solutions demonstrated its TS-960e PXI test system. Pickering Electronics and Pickering Interfaces exhibited relays and switching systems (Figure 2), respectively, for semiconductor test applications. Tektronix exhibited its Keithley line of instruments suitable for semiconductor characterization and also brought along its new 5 Series oscilloscope. And SL Power, TDK-Lambda, and Versatile Power all exhibited power supplies.
Courtesy of Pickering Interfaces
In addition to Optimal+, companies addressing topics related to yield-improvement and “big data” included Qualtera, PDF Solutions, and yieldWerx.
ITC-related activities concluded with two workshops extending from Thursday afternoon through Friday. One was on machine-learning, AI, and data analytics; the other was the 2nd IEEE International Workshop on Automotive Reliability & Test. The latter gave engineers at companies including Bosch, Renesas, Xilinx, STMicroelectronics, Intel, and Infineon the opportunity to describe their use of many of the products highlighted during the week at ITC.
Kevork Kechichian, senior engineering VP at Qualcomm Technologies Inc., delivered the workshop’s Friday keynote address. He described the car of the future as connected, self-driving, highly personalized, and efficient. Kechichian said he has spent his entire career in semiconductors, and although his background is not in test, he has managed test groups. He said he was looking forward to Qualcomm’s planned acquisition of NXP and the resulting potential to push further into automotive products.
There was little emphasis throughout the week on 5G and RF/microwave topics, apart from Roos Instruments’ exhibit. And Prof. Abhijit Chatterjee of Georgia Tech delivered a presentation titled “Beamforming MIMO Systems Using Learning-assisted Performance Optimization.” It described the testing of 5G chips for phased-array massive MIMO applications.
However, the very last paper at the automotive workshop on Friday, from Markus Ulbricht of IHP-Innovations for High Performance Microelectronics in Germany, was on automotive radar test, mostly with application to self-parking and platooning. The topic seemed of interest to attendees, who didn’t drift away, as so often happens to presenters who draw the last slot.
ITC 2018 will be held during the week of Oct. 28 in Phoenix, co-located with the International Symposium for Testing and Failure Analysis (ISTFA).
