What’s All This Talk About Density?

Pickering’s BRIC, higher slot densities can be achieved, with up to 768 relays per slot (Figure 2). To achieve the high densities, the relays must be physically small, with a 0.5-A maximum limit, usable for many small-signal applications. Modules that can switch higher current signals will require physically larger relays, and the resulting density per PXI slot will go down. But the critical point here is that thanks to the advancement in relay technology, switching density has dramatically improved in the past 10 years. This means that switching systems are smaller, assisting the test engineer in keeping the overall test systems smaller and reducing test-floor footprints, which can directly relate to the advantages I referred to earlier. If you are using a modular formfactor such as PXI, greater switching density can mean that you don’t have to purchase that additional modular chassis for instrumentation because switching took up too many slots.

Putting more relays on a switch module results in shorter paths on the PCB, and as paths get shorter, the usable bandwidth increases. Furthermore, more relays on a module mean less external wiring is needed. For example, to construct a 16x32 matrix using a 16x16 module as a building block, two modules are required along with 16 external wires. But as switching density has increased, 16x32 modules are available, eliminating the need for external wiring. Reducing wiring length is especially crucial in RF applications where long signal paths result in attenuation/loss of power.

It is important to note that higher density designs typically require that signal-carrying traces on the PCB be placed closer together; this accommodates the increase in relay count, which can increase channel-channel crosstalk.

Now let’s see a few applications that benefit from a high-density switching system.

Semiconductor test

For years, IC chips have been getting more complex, and consequently, so have the test systems that verify the operation of these chips. That complexity comes at a cost—several million dollars per tester is not out of the question. As a result, chip manufacturers are always looking for ways to lower their cost of test. True,

there is still a need for those multimillion-dollar systems for complete chip and wafer validation, but most of these devices can be tested in simpler ways once good manufacturing quality has been achieved.

It turns out that many analog tests can be set up using a very large matrix (Figure 3), a pulse generator, and one or more SMUs (source/measure units). Now, I emphasize a large matrix because of the sheer number of test points on a wafer or pins on a device—1,000 connections at any one time is typical today.

The testing we are talking about here is aimed at characterization and validation of wafers and chips/dies in product development and NPI (new product introduction). Here are some of the tests used:

Wafer-level test can test for shorts/opens and capacitance.

IDDQ testing is a method for testing CMOS integrated circuits for the presence of manufacturing faults. It relies on measuring the supply current (IDD) in the quiescent state (when the circuit is not switching, and inputs are held at static values). The current consumed in this state is commonly called IDDQ for IDD (quiescent) and hence the name.

For chip-level as well as wafer testing, there is I-V testing for transient charge trapping. One version of this test is called SPCT (Single Charge Pulse Trapping). SPCT uses a pulse generator to do fast I-V curves to either avoid charge trapping or measure charge trapping as a function of a device’s switching frequency. With some modeling work, SPCT can distinguish the initial charge-trapping centers from those created later by voltage stresses.

One important thing to note is that in many of these tests, a large number of test points must be connected to ground to provide a stable test environment. So, it is essential that the matrix you select should be able to close a large number of the matrix’s relays simultaneously. The number of relays will depend on the product you are testing.

Board test with multi-up fixtures

With the IoT and the trend to increasingly miniaturize electronic devices, PCBs are also decreasing in size. Now it is often not practical to individually manufacture—much less test—a 1-in.-square PCB. Hence, such PCBs are assembled in a panel, also called an array. These PCBs are usually tested as a group as well. Once testing is complete, the panel is broken up and the good PCBs are sent on to the next stage of the system assembly. Failed PCBs are either scrapped or sent to rework.

In this case, a large matrix is ideal to share resources between each DUT. In Figure 4, you see several DUTs connected to the X-axis of a crosspoint matrix. A number of instruments are also connected to the X-axis. The colored lines show a number of simultaneous instrument connections. The number of connections is limited by the number of Y-axis lines available. Once measurements are made, the matrix can reroute the instruments to other DUTs and repeat the measurement made earlier.

Board test with multiple test programs

If you are in a repair-depot environment, or a company that has a high-mix, low-volume manufacturing strategy, chances are your test system needs to be very versatile to address multiple DUT types on the same system. For functional test, chances are that many of your DUTs use the same connector types. However, the signal requirement on any given connector pin can be different depending on the function of a particular DUT. (See Figure 5. Note the three different cable connectors for DUT connections.)

This type of situation is where a crosspoint matrix can make your test system much more flexible as it can connect every test resource to any DUT test point, rerouting resources programmatically.

Conclusion

There are many test strategies that depend on the type of test to be performed, volume and mix of DUTs, and your budget. Clearly, no one test system can do it all, at least not economically. But if you have testing needs similar to what has been described here, a crosspoint matrix may be an important part of your test plans.

REFERENCES

“Iddq testing,” Wikipedia.

Rubin, Dave, “Short Pulse Testing Mandatory for Semiconductor Reliability,” Keithley Applications Note, 2006.

“Pickering Interfaces LXI High-density Matrix Modules Selected for Opens and Shorts Testing of Semiconductor Packages,” Pickering Interfaces Knowledge Base.

SwitchMate, 2nd edition, Pickering Interfaces, 2019.

Bob Stasonis is a technical product specialist at Pickering Interfaces. He has contributed to and written numerous papers and articles on the subject of electronic test. Over the last 40 years, Bob has held technical, sales, and marketing positions with Teradyne, GenRad, and Schlumberger. Bob is the president of the PXI Systems Alliance as well as a past board member of the LXI Consortium and past VP of marketing for the American Society of Test Engineers. [email protected]