Cost Control Weighs Heavily On The Minds Of ATE System Makers

June 16, 2003
Faced with testing highly complex system-on-a-chip (SoC) ICs and ASICs that demand more sophisticated test equipment, manufacturers of automatic-test-equipment (ATE) systems are looking for ways to suppress costs. These so-called "big iron"...

Faced with testing highly complex system-on-a-chip (SoC) ICs and ASICs that demand more sophisticated test equipment, manufacturers of automatic-test-equipment (ATE) systems are looking for ways to suppress costs. These so-called "big iron" systems have always been on the pricier side, but a rising chorus of complaints from silicon IC manufacturers is forcing ATE system manufacturers to come up with new strategies. They now offer low-cost versions of more expensive systems via scalable platforms that meet minimum test requirements but can be expanded later to meet changing testing needs.

In addition, test equipment manufacturers are working closely with design-automation firms to lighten the testing burden on the latest-generation ICs. Design-for-test (DFT) techniques are being investigated to make it practical to test these devices at an economic level.

At the same time, a number of low-cost "bare-bones" ATE system vendors are entering the test market with very inexpensive but basic systems. This further increases the pressure on traditional ATE system manufacturers to bring down costs. In between these bare-bones systems and the highest-cost systems lies a number of offerings from companies that provide dedicated test platforms, DFT-oriented systems, and combinations of both.

Still, ATE systems hold a relatively high price tag, often reaching into the range of hundreds of thousands of dollars to $1 million or more. Those dollar levels are significantly lower for some bare-bones systems, which can be had for under $100,000.

In the beginning, ATE systems were dedicated to either digital or analog functions. Thus, one could buy ATE systems specifically to test logic, memory, CPUs, or op-amp circuits. However, the proliferation of mixed-signal ICs that embed memory, logic, and analog signals has forced ATE system makers to come up with more affordable general-purpose testers.

But true testing of complex ICs like SoC devices with clock rates escalating into the gigahertz range requires a different approach. One example is the collaborative effort that Agilent Technologies (www. agilent.com), an ATE manufacturer, has made with Synopsys Corp. (www.synopsys.com), an EDA software provider, to get a better handle on this problem.

Eventually, the future of ATE equipment makers lies in maintaining close working relationships with EDA software companies. Greater collaboration between them can improve the manufacturing test environment. These advances can dramatically reduce the cost of test and lead to a new generation of DFT-based ATE systems, resulting in higher-speed and more accurate ATE systems at an affordable price.

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