Built-In Self-Test Streamlines Testing Of Mixed-Signal SoCs

July 9, 2001
Histogram-based BIST techniques harness on-chip resources to reduce test times and cost while keeping pace with increased circuit complexity.

As the integration between digital and analog circuitry in-creases in system-on-a-chip (SoC) designs, the challenge of testing these mixed-signal functions be-comes increasingly complex in terms of test development time, automatic-test-equipment (ATE) complexity and cost, and production test times. There are some built-in self-test (BIST) methodologies available today that enable the analog portions of an SoC design to effectively test themselves. They also can report results in digital format, minimizing the impact of this increased integration.

This reduced impact is particularly true for analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and voltage-controlled oscillators (VCOs). Employing a technique called histogram-based analog BIST (HABIST), the results of analog circuit tests can be converted to digital test results. The resulting digital data can then be analyzed for such parameters as integral and differential nonlinearity, gain and offset errors, effective least-significant bit (LSB), and clipping and modulation distortion.

During an HABIST implementation, essential information about the signal under test is converted to a histogram, from which characteristics can be studied to gain valuable information about circuit performance. The sample-and-hold circuit and the ADC perform the conversion from the analog domain to the digital domain (Fig. 1). Once the data from the ADC is fed to the histogram generator, the results can be downloaded and read by a digital ATE system.

The technique uses undersampling of the analog signal(s) under test to quantify how long the signal remains at each amplitude level, placing the values in various bins in a histogram (Fig. 2). The histogram characterizes the waveform of the signal under test, capturing its essential elements.

Using software simulation tools, an ideal histogram for each signal under test can be created, as can histograms for signals due to certain defects, like stuck bits and various types of nonlinearity and distortion. These signatures for various types of faulty circuit behavior can be stored for use in determining the pass/fail status of analog circuits under test during production testing.

Should the signal under test vary from the expected signal, the histogram normally undergoes significant changes (Fig. 3). The clipped sinewave shown doesn't spend nearly as much time at the high and low boundaries. Therefore, the resulting histogram has fewer entries in the outside bins and many more entries in the bins adjacent to them. Subtracting the acquired histogram from the ideal histogram creates a difference histogram that can be analyzed to determine which defects are present in the circuit under test.

In addition, the histogram-based method can be deployed to test the ADC that's part of the circuit itself when a proper stimulus signal, usually a ramp, is applied to its input. The ramp signal can be supplied either by an external signal generator or by a DAC that might already be present in the design (Fig. 4). Multiplexers at the DAC inputs and output allow it to be employed not only for on-chip functional purposes, but also as the stimulus generator for ADC testing.

The results from the histogram-based BIST circuitry can be accessed by a digital-only ATE, offering significant savings in cost as well as complexity. The IEEE-1149.1 (standard protocol from JTAG for Joint Test Action Group) testability bus interface, normally included in the design to provide access to the on-chip boundary-scan circuitry, can be used to access the HABIST results. (Boundary-scan circuitry enables interconnect testing during board assembly.) These are placed in a user-defined test data register and accessed by the standard 1149.1 protocol.

The same histogram-based technology applies to DACs. It can solve the many problems that designers encounter when the DAC is embedded in a complex SoC design.

Traditionally, DACs have been tested by successively applying all of the digital codes to the DAC input signals to cause the analog output of the DAC to swing over its entire range. Analog instruments are then typically used to measure the DAC output voltage in response to each input code. These discrete measurements are examined to determine the gain and offset parameters of the DAC under test and to calculate its integral and differential nonlinearity.

Some common problems are associated with these traditional methods. A mandatory test time is required to fully exercise all of the DAC codes. Other problems include analog instrument-measurement errors, settling times, and the controllability of the DAC digital inputs. All of these issues can be addressed with a variation on the basic HABIST methodology.

Let's refer to the previous example configuration (Fig. 4). After the ADC is tested through the HABIST implementation, the tested ADC can be used as the on-chip measurement instrument for any embedded DACs to be tested. A multiplexer at the DAC output routes the signal under test to the integrator and comparator circuitry. Next, the BIST circuitry simply treats the DAC output as another analog signal to be evaluated, reading the data digitally and analyzing it by histogram methods.

Alternatively, if no sample-and-hold and ADC circuitry is available on-chip for this purpose, a dedicated DACBIST circuit can be implemented (Fig. 5). For test purposes, the test control circuitry permits the replacement of the DAC inputs by code-pair combinations that will exercise it as required. Switched capacitors alternately sample the reference voltage, derived on-chip, and the DAC-under-test output voltage. The comparison results are fed to an up-down counter. Typically, this counter is 4 bits wider than the number of DAC input bits to obtain maximum accuracy. The output from the counter is stored in the Result register as digital data.

There are significant test-time advantages to using a BIST approach for DAC testing. A comparison of traditional ATE test times and BIST test times for various DACs based on the number of bits in the DAC implementation is shown in Figure 6. As the chart illustrates, unless the DAC under test is very precise (16 or 18 bits), the advantages of short test time and, therefore, lower test cost offered by using a BIST approach are very significant. Also, with this technique, the DAC can be tested at its full operating speed, so it can be checked for both its static and dynamic operating characteristics.

As device speeds continue to increase, timing accuracy be-comes a much more critical factor for both clocks and data circuits. Timing budgets are tightening and thorough testing of phase-locked loops (PLLs) and VCOs are becoming more important too. The most significant parameters that must be tested for PLLs and VCOs are for various kinds of jitter—peak-to-peak (p-p) jitter, root-mean-square (rms) jitter, and long-term jitter.

Traditional methods for testing these values include time-interval-analyzer and counter-timer solutions. These methods are based on traditional ATE systems equipped with mixed-signal capability in the form of specialized and expensive instrumentation.

For VCOs and PLLs, a BIST technique implemented with a pair of ring oscillators can be used to measure true p-p jitter and rms jitter (Fig. 7). In operation, the two ring oscillators are set to different frequencies, the second slightly higher than the first. Both oscillators begin at the same time and eventually coincide with each other on a specific edge of the signal under test. At this juncture, the coincidence detector stops the measurement cycle, and the results are read from the serial scan register as digital data, eliminating the need for expensive and time-consuming analog instrumentation.

Constructed of simple inverters connected in a controllable feedback configuration on-chip, the ring oscillators can be "tuned" to the correct frequencies (normally about half the frequency to be tested) for maximum test speed and accuracy. This BIST technique self-calibrates before each jitter measurement and doesn't require an external low-jitter reference signal. The technique has the advantage of running at full device operating speed.

Moreover, it's not subject to the measurement errors that can occur when the assumption is made that all jitter exhibits Gaussian behavior, which frequently doesn't happen. Using BIST for jitter measurements can conserve much of the requisite test time. The time required for each measurement decreases as the device speed increases.

When this VCO-based BIST technique is combined with the histogram-based technique, it's possible to write code for a PC that will display the test results (Fig. 8). Or, they may be downloaded to a digital-ATE system for analysis. Alternatively, the comparison can be implemented completely on-chip.

This VCO-based BIST technique has been implemented, for example, on a 500-MHz programmable PLL by Infineon Technologies AG, Munich, Germany, with its 0.18-µm advanced CMOS process. Another advantage of the VCO-BIST technique is that its speed, resolution, and accuracy keep pace with increasing device speed. In fact, this VCO-BIST technique has no theoretical limits.

As mentioned previously, the results from the histogram-based BIST circuitry can be obtained with digital-only ATE for major reductions in cost and complexity using the JTAG testability bus interface. Normally, this interface is included in designs to provide access to the on-chip boundary-scan circuitry. The histogram-based analog BIST results (either go/no-go or actual measurement data) are placed in the user-defined test-data registers provided by the JTAG architecture (Fig. 9). These are accessed using the IEEE-Std-1149.1 protocol.

Implementing the standard test-access port offers significant advantages. Synthesizable versions of the TAP (Test Access Port) logic are widely available, both from design-automation vendors as well as within the intellectual-property libraries of most IC manufacturers. Additionally, almost every digital ATE system today has both the hardware and software in place to interact with TAP logic. This reduces the test-engineering learning curve and makes it easier to get data into and out of the BIST circuitry.

Analog and mixed-signal BIST techniques can often be employed as an alternative to complex and expensive mixed-signal ATE systems. Or, they can be used to augment those systems implementing a distributed test strategy where some BIST circuitry is included in the chip design and some of the processing hardware is placed on the tester's load board. The software can often be similarly distributed.

Designers frequently tout BIST as a complete replacement for ATE systems. In reality, though, it's not a replacement strategy. Instead, it's a very valuable adjunct to extend the life of existing digital ATE systems when new SoC designs include mixed-signal circuit blocks.

The techniques described in this article can be implemented on-chip with minimal silicon. They often result in reduced test-development and debug times, which can speed up time-to-market. Furthermore, shorter production test times reduce product testing costs. Finally, because of its increased fault coverage, BIST leads to higher product quality.


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