Build A 3D Test Method One Die At A Time

Two P1687 SIBs could be deployed back to back and function as an embedded and self-contained two-bit access instruction register, opening and closing the scan paths to provide the four functions needed by P1838.

Sooner or later the laws of physics and Moore’s law have to conflict. Even though that day may be here sooner rather than later, three-dimensional (3D) chips of multiple silicon die stacked on top of one another is one of the most viable means of keeping up with Moore’s law by doubling the number of circuits on one chip every 18 months.

Adding circuits is not a problem for 3D chips, but validating, characterizing, and testing them certainly will be. That’s why the new IEEE P1838 Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits is being developed.

The IEEE P1838 working group’s strategy defines a test access method for one die that’s scalable to a 3D stack of multiple die when more than one die are stacked on top of each other. The group has focused on 3D silicon integration chips where the several die are connected vertically by through-silicon vias (TVS), as opposed to package-on-package or other 3D chip packaging techniques like using bonding wires to connect multiple die in a stack.

Unlike some alternative methods of integrating several distinct die, TSV-connected die provide no external test access to the inter-die interconnects. And since the die in a 3D package are not fabricated to be packaged individually, there are few, if any, test probe pads on them. Furthermore, TSVs will typically be around 2 µm in diameter, much larger than on-die routes. As a result, test pads would be costly to provide.

Ultimately, the optimum solution for 3D chip test is an on-chip test and debug access port. This port would be the most economical solution to the 3D chip test problem because it would require fewer test signals than alternative methods on each die and on the entire stack.

Rather than invent a new test access port, the working group is leaning toward adopting the IEEE 1149.1 boundary scan (JTAG) standard as one possible access solution. Consequently, the P1838 draft standard may appropriate the JTAG test access port (TAP) to make it a part of the P1838 working document.

JTAG In The Basement

In a 3D stack of multiple die, only one die—the base die—will have pins and possibly probe pads because it will be the only die in the stack that will be connected to a circuit board. Because it is connected to the board, this die in the stack will have the IEEE 1149.1 JTAG port for at least the purpose of conducting board test boundary scan.

Even if the base die is an interposer or does not contain any digital logic, it still must support the four signals of the JTAG TAP: test clock (TCK), test mode start (TMS), test data in (TDI), and test data out (TDO). Since both chip and circuit board tests will have to be executed on a 3D chip, P1838 will have access to the base die JTAG TAP and TAP controller as the methodology for accessing, configuring, controlling, and operating the chip’s test and debug logic. This would require all of the die in the stack to be compatible with JTAG-based control signals.

An analysis of the test and debug requirements applied on a per-die basis has resulted in the identification of four access operations. The four basic scan path operations that each die in a 3D chip must support are:

• Bypass: Skip this die without accessing any on-die functions.
• Turnaround: Terminate the scan path at this die and return the scan path downward.
• On-die access: Access the test and debug logic contained on this die.
• Next-die access: Access the test and debug logic on the die above this die while maintaining access to the current die.

The turnaround function should be the default operation following an IEEE 1149.1 boundary scan reset—that is, when the JTAG finite state machine (FMS) is passed through the test logic reset (TLR). This will ensure the shortest scan path through the 3D chip and allow for the path to be accessed and operated even if the per-die bypass function is broken on one of the die in the stack. If the scan path were broken on one of the die, then each die could still be added to the scan path one die at a time with an alternate path used on the die with the broken scan path.

Under IJTAG Management

Several techniques are being investigated, but in the end the P1838 working group is considering another pair of embedded logic standards. The IEEE 1500 Core Test standard is thought to be the best way to solve the embedded core problem. A preliminary standard approaching ratification, the IEEE P1687 standard for embedded on-chip instruments, is thought to be a way to implement the four access operations and to provide on-die management features and techniques for embedded instrumentation.

The segment insertion bit (SIB) of P1687 can provide an elegant solution for the P1838 group. Two P1687 SIBs could be deployed back to back and function as an embedded and self-contained two-bit access instruction register. This configuration could then open and close the scan paths to provide the four functions needed by P1838 (see the figure).

The lower or first SIB on the scan path shown in the figure can perform two functions. If a logic 0 is placed in its update cell (U), then the path to the upper SIB, or the second SIB in this pair, is activated. If a logic 1 is placed in the update cell in the lower SIB, then the wrapper serial input (WSI) port is connected to the on-die scan path and returned through the wrapper serial output (WSO) path.

Likewise, the upper SIB can perform either of two functions. If a logic 0 is placed in the update cell, then the downward path to the TDO port on the bottom die interface is selected. But if a logic 1 is placed in the update cell, then the upward path to the TDI on the upper die interface is selected and the scan path will extend to the TDO on the upper die interface. In this way, these two SIBs consisting of two bits provide the four functions needed by P1838 (see the table).

It should be pointed out that SIBa or the first SIB in the path should have a multiplexer preceding the shift cell, which would make the distribution of the TDI a loading problem. If the multiplexer were placed after the shift cell, the return path might present a long combinational path problem. A loading problem is preferred because design tools are adept at sizing buffers and drive strength to manage fanout and loading, but they have greater difficulty with managing long combinational paths.

Also note that the figure has been simplified to be more understandable. The Select, ShiftEn, CaptureEn, UpdateEn, and Reset are only shown at the interfaces of the bottom and top dies and not routed through these dies. Showing these routes would have unduly complicated the diagram. If these routes were shown, the Select port would pass into a set of AND gates that enable the other SIB operating signals, ShiftEn, CaptureEn, and UpdateEn.

These SIB operating signals originate either from a tester or from the die stack’s TAP controller. In this way, the test facilities on a certain die in the stack can only be operated when they are “selected” by the tester or the die below it. For example, the Select signal from SIBb in the figure will be used to enable the test facilities in the die above it.

As the IEEE P1838 working group continues its development of this standard, it will evaluate various solutions and judge each one based on whether it meets the needs of the group’s recently adopted and self-imposed criteria developed against “per die” and a “per stack” requirements.  The ultimate goal of the committee is to produce a clean and elegant solution that can be implemented with minimal resources and yet become a fully functional testing framework for 3D die stacks and the individual die in the stack.