After the hype of CES, venturing to DesignCon is the best way to get your geek back on by joining fellow EEs as they tackle the really hard signal-integrity, connectivity, and test issues now facing the industry. This year’s event was no exception, and the emphasis on PAM-4 signal generation and test portends a big year for 200 and 400 GbE.
Extended use of PAM-2-NRZ has delayed the jump to PAM-4. However, the move toward denser 2.5D and 3D packaging and associated higher intra- and inter-chip, board, backplane, and inter-chassis bandwidth requirements, combined with the need to maximize use of currently installed fiber, has invigorated the discussion around PAM-4 (Fig. 1).
While PAM-4’s ability to help deliver 56-Gb/s/channel for 400 GbE is exciting, achieving those rates is not without its fair share of difficulties. These include higher signal-to-noise (SNR) requirements to accommodate the four distinct signal levels (0, 1, 2, 3). This is helped by the application of forward error correction (FEC) to relax the bit-error-rate (BER) requirements, but FEC implementations vary and give inconsistent eye diagrams.
That said, the use of FEC will increase and the consistency will improve, since it’s easier and cheaper to throw processing power at the problem than to fully optimize the entire signal channel. A simple analogy is high-end audio systems: DSPs helped implement relatively high-quality surround-sound audio using digital sensing and compensation techniques. This got around the need to invest in thousands of dollars of audio equipment and room acoustics. It’s not exactly audiophile level, but for most consumers, the audio effect is sufficient.
To show the cutting-edge of PAM-4 signaling, Teledyne LeCroy’s vice president of Technology Development, Peter Pupalaikis, delivered a paper around the demonstration of a prototype 190-Gbaud (380 Gb/s), electrically generated PAM-4 signal. This is the fastest to date and came about as result of collaboration with Nokia Bell Labs. It required a lot of work in the areas of signal processing, microwave-frequency hardware, and equalization. Nokia is a good example of a company that would much rather invest in high-speed processing on the silicon side than uproot and replace its installed fiber.
On the show floor, Teledyne LeCroy demonstrated fully automated transmitter testing for 56-Gb/s PAM-4 using its new QPHY-56G-PAM4 option. Available on LabMaster 10Zi-A oscilloscopes, the PAM-4 option is part of the company’s QualiPHY automated-test-compliance platform.
The new option adds standards-specific measurement capabilities based on the OIF CEI-56G-PAM4 and relevant PAM-4-based IEEE 802.3 interface standards. Measurements include eye diagrams, eye widths and heights, linearity, signal-to-(noise + distortion) (SNDR), transition time, linear fit pulse peak, and equalizer measurements (Fig. 2).
QPHY-56G-PAM4 will initially be available with transmitter test coverage for the OIF CEI-56G-VSR-PAM4 interface standard (both host- and module-output test points). Coverage will expand to include –MR and –LR variants of OIF-CEI-56G-PAM4, as well as IEEE 802.3bs and 802.3cd Ethernet standards.
Plethora of PAM-4
PAM-4 waveforms were everywhere: Tektronix showed NRZ/PAM-4 (100 Gb/s, 400 Gb/s) testing tools for its DPO70000SX 70-GHz scope, while Rohde & Schwarz demonstrated VNA-based PAM-4 measurement capability on its ZNB 20 20-GHz VNA (Fig. 3). Chris Scholz, product manager at Rohde & Schwarz, said that the demonstrated capability is a first for its VNAs and would be available soon.
Tektronix also put its new BSX series on display at the booth. The BERTscopes are the first 32-Gb/s, protocol-aware BER testers (BERTs) for fourth-generation protocols such as PCIe 4.0, USB 3.1, and SAS4. The BSX series scopes visualize and control the handshaking and link training process for devices running up to 32 Gb/s to help designers get a better insight into the underlying cause of specific receiver bit error rates by capturing the exact location and timing of errors.
Going back to PAM-4 again, Keysight Technologies’ master engineer Robert Schaefer gave a whirlwind demonstration of the company’s Physical-Layer Test System (PLTS) for PAM-4 (100 to 400 Gb/s) test, as well as the very useful channel operating margin (COM) tests, and automated high-speed cable test. Bob explains it best here:
The PAM-4 signal simulations are actually based on S-parameter measurements made by the user. The video clearly shows all four levels and the three interdependent eye diagrams.
The COM measurements idea, which came from Intel, gives a quick, single-number evaluation of a cable’s characteristics. As was often the case, a cable would fail some parametric tests, but still be able to carry the required high-speed signals, in this instance, PAM-4.
The automated test features SCPI-programmable, 32-channel, high-speed cable test capability. Officially called the Digital Interconnect Test System, Reference Solution, the feature is based around Keysight’s M937XA PXIe VNA and includes full signal-integrity characterization, multi-domain analysis, crossbar calibration, and a customized API to synch with PLTS to simplify and accelerate test.