White Paper from Design Con 2017: Accurate Statistical-Based DDR4 Margin Estimation using SSN Induced Jitter Model

With increasing switching speeds and lower supply voltage, DDR memory design engineers are challenged by the distorting effects of noise and jitter. It becomes very difficult to meet the ultra-low standard BER requirements.

A new statistical simulation approach extracts the jitter model from the voltage noise. Read more.

Download white paper now.