Electronic Design

DFT Compiler/ATPG Tool Combo Aids In DFT

The integration of DFT Compiler in the physical compiler environment facilitates design-for-test (DFT) closure. According to the manufacturer, this addition enables fast timing closure with fully testable semiconductor designs.

Also, the company increased its use of next-generation sequential automatic test-pattern-generation (ATPG) technology through the creation of the TetraMAX ATPG tool. Combined, the products yield the DFT closure and increased pattern-generation power needed to test complex systems-on-a-chip.

The inclusion of DFT Compiler in the physical compiler environment optimizes scan DFT without cumbersome scripts and data transfers. Using placement information, this device employs a constant-driven scan-ordering algorithm to optimize scan chains within the physical synthesis environment. The risks of routing congestion and timing violations that may arise from DFT without physical information are avoided by the tight integration of scan ordering and physical synthesis. According to the company, routing congestion can be reduced by an average of 10% to 15%, with noticeable improvements in overall timing.

By eliminating the need for reformatting ATPG vectors, the automatic flow between the DFT Compiler and the TetraMAX ATPG is significantly improved. The latter device is comprised of an ATPG engine plugged into a multitechnology architecture. This configuration lets designers reach their manufacturing fault coverage goals for a broader range of circuits, including near-full-scan designs with nonoptimal testability.

Since the process is completely automatic, designers reach their test manufacturing program requirements without additional setups or output modifications. In some cases, testability in large designs is reduced by the need to remove elements from the scan chain to achieve timing closure and optimal scan-chain ordering. In such cases, TetraMAX transparently invokes the advanced sequential engine's extra ATPG power to compensate for the reduced testability.

Both products will begin shipping in this month. Current customers will receive these enhancements at no additional charge as a maintenance upgrade. DFT Compiler costs $15,000 and TetraMAX ATPG costs $35,000 for one-year technology subscription licenses.

Synopsys Inc., 700 E. Middlefield Rd., Mountain View, CA 94043-4033; (650) 962-5000; fax (650) 965-8637; www.synopsys.com.

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