Electronic Design

Digital Test System Gets Speed Bump From Clocks

High-speed clocks added to the high-channel-density/low-cost SR2500 Digital Test Subsystem can be two to four times faster than the data rate of the instrument. The SR2500 supports both serial and parallel testing of standard transistor-transistor logic (TTL), differential TTL, differential emitter-coupled logic, low-voltage differential signaling, variable-voltage, or 5-V CMOS logic devices or systems with up to 576 individual input and output pins. The unit also provides high-speed digital pattern generation, response comparison, logic analysis, and optional guided probe and fault diagnostic capability. The SR2500 offers RAM-backed and algorithmic pattern generation, programmable edge placement, per-pin data formatting, and up to 256-kbyte vector depth. Additional features include multilevel triggering and advanced logic analysis, as well as real-time pattern comparisons for pass/fail indication and decision-based testing. The SR2500 Digital Test Subsystem with high-speed clocks costs $13,900.

Interface Technology Inc.
www.interfacetech.com; (909) 595-6030

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