Electronic Design

Dispatch #2 From DATE 2005

MUNICH, March 8 — The opening day of 2005's Design Automation and Test in Europe (DATE) Conference has come and gone, and it was a surprisingly busy show by anyone's measure. Europe's engineering community has come out in force—in snowy, bleak weather, no less—to look the EDA industry up and down and see what it's got to help them design their way out of the doldrums.

What they found was a broad palette of technologies, tools, and methodologies, much of which is homegrown right here on the Continent. Sure, when you think of EDA, you think first and foremost of places like San Jose, Mountain View and Wilsonville. But don't count out Freiburg, Germany or Cergy-Prefecture and Montbonnot in France. Although the Black Forest is perhaps best known for cake and cuckoo clocks, there's interesting EDA technologies coming from off the beaten track that shouldn't be overlooked.

More From the ESL Front
As was mentioned in yesterday's dispatch, Europe is indeed a stronghold for system-level methodologies. ESL devotees who've made their way to Munich haven't been disappointed. One of the most interesting pieces of ESL news today came from Sequence Design. Yes, that Sequence Design, the one that is by and large oriented toward power integrity in the physical domain. But according to Sequence's president and CEO, Vic Kulkarni, Sequence is pushing its way into the ESL arena.

Recognizing that the greatest power savings can be realized in the front end of the design process, Sequence has extended its PowerTheatre tool into the ESL domain to enable system-level power analysis. At ESL (meaning at transaction level), a five-second cellphone call can be analyzed in hours. At RTL, that same analysis might take three months or more. Moreover, Sequence claims they can achieve this with 30% accuracy compared to gate level.

Watch for a further announcement from Sequence in the DAC time frame regarding power integrity analysis and optimization in the place-and-route loop. The company will be challenging for leadership in dynamic voltage-drop analysis with technology that brings ±5% accuracy compared to HSpice. It'll do so while running in excess of 20 Mgates in just 16 hours.

ESL is more real to some designers than to others. There are those for whom it's an interesting idea, and then there are those who've actually plied the waters of starting with a design representation that is somewhere less concrete than fully timed, bit-accurate models. For the latter, an interesting issue arises: No matter where you started from on the continuum of ESL, as broad as that is, you eventually found your way to RTL. How do you know that the RTL you ended up with is functionally equivalent to your ESL description?

Startup Calypto Design Systems thinks it has this problem solved in a technology that will soon see commercial release. Centered on what it's calling sequential equivalency checking, Calypto plans to give designers a tool that will allow them to design and verify at abstraction levels above RTL. "Although many design teams have not 'officially' adopted system-level flows, they're already moving up in abstraction," says Calypto's CEO, Devadas Varma. "They do so when they make design changes such as retiming, pipelining, state re-encoding and resource sharing in order to meet power or timing goals. In the process, they also change the sequential nature of the original design, which by default moves them up from RTL in terms of their sequential level of abstraction. "

Changes of this kind haven't been well supported in standard design flows. The problem is that designers know this, and as a result, they often don't make changes that they suspect they should make. Calypto's technology will give them the confidence to make these changes by allowing them to navigate between these subtly different levels of abstraction. Designers can make their changes, verify them, and then retarget the design toward final RTL implementation.

Although it's not exactly new technology, virtual prototyping is still making its ways into design flows. Virtual prototyping is known to greatly reduce system silicon design time in complex applications such as high-definition digital TV and 3G mobile phones.

ARM chose DATE for the debut of its RealView ESL tools support for ARM11 family-based system prototyping. The RealView ESL tools operate at the cycle- and transaction-based abstraction level to enable a complete virtual platform for modeling and programming multi-core SoCs before silicon sees a mask set.

The RealView Model Library, which incorporates MaxLib SystemC models, includes cycle-accurate models of all ARM11 family uni-processors, as well as models of other configurable system components which use the AMBA 3 AXI interconnect protocol. These include: the ARM PrimeCell AMBA 3 configurable interconnect (PL300), the PrimeCell dynamic memory controller (PL340), and the PrimeCell Level 2 cache controller (L220), as well as a complete set of bridge components enabling the easy connection of existing peripherals and bus models which use AMBA 3 protocols.

Getting the Bugs Out
Few of the companies at the Design Automation and Test in Europe match the conference's name and intent better than France's Temento Systems, which markets design and test automation products for debugging of everything from SoCs to FPGAs, boards, multichip modules and full systems. At DATE, Temento rolled out a new version of its DiaLite debug tool that includes a Property Specification Language (PSL) assertion checker module. This module effectively translates PSL assertions into IP and puts them directly into silicon, enabling at-speed property checking.

The module supports PSL v1.1 and enables complex PSL expressions to be associated with triggers. It combines DiaLite's existing ability to create instrumentation IP with PSL assertions, allowing designers to take advantage of PSL's incremental analysis capabilities. Progress can be made in debugging without having to resort to multiple synthesis loops.

Release 4.5 of the DiaLite Platform Edition runs under Windows XP, 2000/NT and Solaris. Licenses start at 15,000 Euros.

Concept Engineering, based in Freiburg, Germany, is one of a handful of EDA companies that markets its products both to end users and to other EDA vendors for incorporation into their tools as well as to IDMs for use in their in-house flows. Concept's products facilitate generation, display, and customization of schematics from Verilog, EDIF netlists, or Spice descriptions of circuits.

At DATE, Concept announced the sixth entry in its series of visualization software components. NLViewWX is an engine that fits into the company's wxWidget environment to give EDA tool developers an easy-to-use programming interface for writing GUI applications. An evaluation kit will be ready to go in the second quarter.

Concept also offers its visualization engines to end users in the form of SpiceVision, for debug and analysis of Spice circuits and models, and GateVision, for use with gate-level descriptions. The latter offers the ability to mix and match transistor- and gate-level models.

Foundry Partnership
Collaborations between EDA tool vendors and foundries are an increasingly important part of the design flow. Without them, it's unlikely that design teams would ever achieve correlation between models and silicon. The increasing analog and mixed-signal content on SoCs is exacerbating this problem in the non-digital world. That's why Cadence has expanded its foundry partner program to collaborate with German foundry X-FAB. The pair will build and deliver comprehensive design kits for analog and mixed-signal ICs targeting mainstream and advanced process technologies.

Fully qualified mixed-signal design kits, including physical verification runsets for Cadence's mixed-signal design flow, are offered through X-FAB's online service, X-TIC. PDKs from X-FAB are available for all offered technologies from 1.0 micron down to 0.35 microns, with voltage ranges from 1.0 V up to 650 V on CMOS and BiCMOS processes. Each process family has add-on modules that offer a broad variety of process combinations.

Related Links

Cadence Design Systems

Calypto Design Systems

Concept Engineering

Sequence Design

Temento Systems

X-FAB Semiconductor Foundries AG

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.