Electronic Design

Generator-BERT Combo Simplifies Jitter-Tolerance Testing To 12.5 GHz

With 5-Gbit/s and better serial bus standards coming soon, design and test of the next generation of serial bus devices will feature a cast of significant signal integrity and jitter issues. New transmission techniques, like spread-spectrum clocking, will make device characterization more difficult.

The answer, in Agilent Technologies' view, is the N4903A serial bit-error-rate tester (BERT) with advanced jitter-generation for jitter-tolerance testing of serial devices at up to 12.5 Gbits/s (see the figure). This one-box solution provides calibrated jitter composition and automated characterization. It complies with all popular serial bus standards, including PCI Express, SATA, Fibre Channel, FBDIMM, CEI, Gigabit Ethernet, and XFP. Designers can perform fast, high-precision stressed eye testing with more than 50% eye closure. For clean eye testing, the unit features 20-ps transition times and 50-mV analyzer sensitivity. The BER and measurement suite includes BERT scan, output timing jitter, spectral jitter decompsition, eye contour, fast eye mask, output level and Q factor, and error-location capture functions.

The N4903A fully supports the complex data patterns of serial bus interfaces. Unpredictable traffic can be analyzed with the bit-recovery mode, which allows more realistic test scenarios. Built-in clock data recovery capability, new substrate clock outputs, and spread-spectrum clocking significantly simplify the clock setup.

Prices start at $120,000 for the 7-Gbit/s version and $160,000 for the 12.5-Gbit/s version.

Agilent Technologies Inc.

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