When creating a manufacturing test set for digital designs on technology feature sizes of 130 nm and smaller, it's important to include at-speed tests. Stuckat tests have been used for many years and continue to catch a lot of manufacturing defects. However, at the smaller feature sizes of today's chips, more and more defects are timing related and aren't caught by the stuck-at test patterns.
The most common at-speed tests are created using the transition fault model in automatic-test-pattern-generation (ATPG) tools. This model looks for slow-to-fall and slow-to-rise transitions on every node in the design.
The problem with adding transition test patterns to the stuck-at pattern set is that the transition-test-pattern volume is typically three to five times larger than the stuck-at volume. When the two test sets are combined, the total volume can exceed the amount of tester memory available. While some designers choose to truncate the pattern set to fit on the tester, this leads to reduced test coverage and product quality.
The better solution is to add on-chip test compression logic so that the tester need only hold compressed stimuli and expected responses. A good compression solution can handle the design's X (unknown) states automatically and can reduce the test time as well as the tester memory requirements.
This design tip was provided by Bruce Swanson, technical marketing engineer for Mentor Graphics.