The proliferation of high-speed digital serial links is causing all kinds of test-related headaches for designers. The measurement requirements for these high speeds are different from those for typical digital debug and rather resemble what’s needed for RF test.
A quick look at a PCI Express (PCIe) eye diagram would tell you that. The same goes for USB 3.0, which clocks at 5 Gbits/s. Creating sharp-edged pulses at these speeds is a major challenge. The physical-layer challenges posed by PCIe 3.0 are considerable as well. (For more, see www.pcisig.com/news_room/faqs/pcie3.0_faq/.)
“At 8 GT/s, eye diagrams are completely closed,” says Jun Chié, marketing manager for Agilent’s digital-debug solutions product line. “As signals come through on the transmit side, we have to perform equalization to open up the eye so that we can find the right probing points to capture samples and measure them.”
It’s the same story on the receive side of a link. Further, jitter components are more important at these signal speeds. For scope users in digital designs, the most popular measurement is jitter analysis. This and crosstalk are now more important on the digital side than they ever used to be on the analog side. These features are most popular in today’s scopes.
Another emerging issue in the debugging of PCIe 3.0 links is signal degradation in the transmission line. One can examine the signal out of the transmitter and verify that the eye pattern looks good and that jitter is within specification. But a PCIe signal can travel a maximum distance within a system of 16 inches. When it arrives at the destination receiver chip, the eye pattern is closed once again.
“We haven’t tested much in the past for receivers, but now we have to do that,” says Chié. “There’s now a requirement to determine whether the receiver port can tolerate signals coming through.”
Agilent has been building up a complete test suite for PCIe 3.0. For the testing of PCIe 3.0 receiver ports, the company offers its N4903B J-BERT, which is used to inject jitter on the receive side of a PCIe link to simulate less than optimal conditions.
“The critical element on the transmit side is jitter and crosstalk,” says Chié. “The N4903B J-BERT precisely injects known jitter components into the receiver. By doing so, we can check on the physical level to see if the receiver can tolerate the jitter.”
The N4903B has recently been augmented by the release of the N4876A, a 2:1 multiplexer that extends the J-BERT’s data rate up to 28 Gbits/s. To further improve the N4903B’s utility for receive-side testing in USB 3.0 applications, Agilent has added a second output channel that enables the instrument to support USB 3.0’s tri-level mode.
“To generate and stimulate the low-power mode in USB 3.0, we need to generate three different signals. The two outputs used in combination generate that third level,” says Chié.
The latest element in Agilent’s PCIe 3.0 test suite is its Digital Test Console (see the figure), a complete and integrated x1 through x16 protocol analyzer and exerciser for the PCIe 3.0 protocol specification.
“With an oscilloscope, you use a trigger point to trigger on a certain signal and capture it for analysis,” says Chié. “Protocol analyzers have to behave like a real signal, equalizing it in real time and linking with the DUT (device under test) properly.”
To this end, the Digital Test Console features a proprietary Agilent ASIC that uses equalization snoop probe (ESP) technology for reliable data capture at 8 GT/s. The technology accounts for a wide spectrum of losses when probing at different points on the bus. It provides auto tuning to account for being plugged into any location in the channel. It also compensates automatically for probe cable losses. The result is a properly equalized signal at 8 GT/s with a usable eye diagram.
Additionally, the console incorporates a link training and status state machine (LTSSM) exerciser to validate new encoding and protocol state-machine designs. “Intel and other chip companies are still working on chips to generate PCIe 3.0 protocol schemes, and they’ll be coming this spring,” says Chié. Meanwhile, developers of PCIe 3.0 bus systems need a way to emulate their DUTs to see if they comply with the specification. The Digital Test Console’s LTSSM exerciser delivers the means for doing so.
Agilent’s Digital Test Console for PCIe 3.0 is available now, with an average system price of $100,000.