Electronic Design

Logic Analyzer Option Simplifies DDR2 Testing

Debuting as a complete DDR2 protocol debug and validation solution for the TLA6000 Series Logic Analyzers, options for the series consist of everything necessary to validate and debug the operation of memory sub-systems. The options consist of a set of tools designed to provide visibility to all address, data, and control signals. The bundle includes memory chip interposers for probing embedded DDR memory systems, protocol decode software that shows all DDR2 transactions as well as providing triggering on DDR2 events, sample point analysis software that automates the process of correctly configuring the TLA6000 Series to sample the DDR2 signals, and protocol violation software that finds and reports any violation of the JEDEC-defined DDR2 protocol. Pricing starts at $9,110 for the DDR2 Protocol Debug and Validation Toolkit. TEKTRONIX INC., Beaverton, OR. (800) 426-2200.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.