At $399,000, the 93000 SoC (system-on-a-chip) DFT (design for test) series promises users a one-cent-per-second cost of test. As such, this version of the Agilent Technologies 93000 SoC platform would become the most cost-effective SoC DFT solution available.
"It started over two years ago with our EDA partnerships, work on standards, and the recent introduction of our SmartTest PG CTL browser and will continue as we deliver additional products and services," says Asad Aziz, product manager of Agilent Technologies' Automated Test Group. "Our goal is to provide a scalable SoC DFT solution that gives users the ability to reap the benefit of their investment in DFT techniques without sacrificing quality or time-to-market."
The 93000 DFT series includes the test processor per pin architecture (TPPA), which allows users to set up cores for independent operation and concurrent test. Ultimately, this will reduce test time by 30% to 50%. The TPPA also provides enhanced capabilities for SoC DFT diagnostics, such as "selective BIST (built-in self-test) capture," to help diagnose failures detected in the test process.
Also, the series includes SmartTest PG CTL Browser. This test-program generation environment directly supports the proposed IEEE P1450.6 Core Test Language (CTL) and other standards. CTL provides a standard interface between EDA and automatic-test-equipment environments, enabling faster turn-on and debug cycles for SoCs and producing faster time-to-market.
The basic 93000 SoC series is configured to span the widest range of applications, with data rates up to 10 Gbits/s. Available for immediate order, its $399,000 price includes 128 channels, SmartTest PG, CTL Browser, Concurrent Test, and consulting and services.
Agilent Technologies Inc.