Reduced test data volume, test run time, and automatic test equipment (ATE) reloads come via VirtualScan software, which ultimately slashes the cost of semiconductor testing. When evaluating a 2 million-gate circuit, the software can potentially reduce test time by a factor of 15. VirtualScan's proprietary, patent-pending compaction technology allows existing ATE resources to apply automatic test-pattern generation (ATPG) patterns through each external scan chain to a user-selectable number of shorter scan chains. Using a larger number of short scan chains reduces test application time and ATE memory storage re- quirements. It also extends the use of existing ATE for larger chip sizes without compromising product quality. On one end of the chip, circuitry is used to broadcast each external scan-input chain to a user-selectable number of internal scan chains. At the other end, additional circuitry compacts the chains into the original number of external scan chains. VirtualScan contains an automatic synthesizer to incorporate the broadcaster and compactor into the scan circuitry. The short scan chains can be virtually accessed from outside the chip with a limited number of pins assigned as scan pins. The software also contains tools for scan insertion and scan synthesis. Pricing begins at $250,000. An upgrade to VirtualScan is available to licensees of the company's TurboScan tool, a scan synthesis and ATPG product.
SynTest Technologies Inc. www.syntest.com; (408) 720-9956