Stronger Than the Slowest Link

Standardisation and advanced tools help high-speed serial-data technologies leap over that “slowest link” hurdle.

Bringing next-generation technologies to market has always required substantial capital outlay plus an optimistic view of the risks involved. Successfully implemented, products based on the new technology offer richer features and higher performance that attract customers and make good returns for the developer.

Today, a new generation of computing, networking, telecommunications, and digital embedded systems rely on advanced processing technology coupled with highspeed serial-data transmission to deliver impressive performance and functionality at relatively low cost. However, we’ve seen substantial increases in capital investment— and risk. Thus, good engineering and project management skills are a must. One also needs the right tools to ensure that the design meets functional, performance, and compliance specifications, and to identify design flaws as early as possible in the process.

High-Speed Serial Pathways
Synchronous parallel buses were the established technical approach for data exchange between digital devices. By moving multiple bits in parallel, these data-bus technologies were seemingly faster than serial-transmission techniques. Unfortunately, timing synchronisation (skew) became problematic at high clock frequencies and data rates, limiting the maximum speed of parallel bus transmissions. Cost of implementation over extended distances was also an issue.

Serial-data transmission, with embedded clocks, solves the synchronisation issue and allows for much greater throughput at lower cost. Serial-data bus architectures are now widespread in digital environments and have supplanted parallel designs for applications with higher speed.

But as one performance barrier gets eliminated through a technology advance, another appears. New and faster technologies, added design complexity, and constantly changing standards create new design challenges that hinder time-to-market and increase development cost.

Ensuring interoperability requires standardisation. Leading technology companies working with standards such as PCIExpress, SATA, HDMI, Infiniband, and others already offer 2.5Gb/s and 3Gb/s designs. But don’t look now, because 5Gb/s technologies are on the way, and 10Gb/s is already in use for network communications. This isn’t “easy” technology— imagine poking a piece of string through a 10-meter length of hosepipe, with bends, kinks, and joints, and expecting it to emerge without deformation at the other end!

With so much complexity and change, engineers need tools to help them identify and correct design problems quickly and easily. Functional simulation tools serve to prove the design concept.

Once the design is layed out, the engineer will likely perform a full 3D electromagnetic (EM) field simulation, at least on the critical high-speed elements. This level of verification was once the preserve of RF engineers, but absolutely necessary now in the digital domain, with contemporary transmission speeds.

The EM field simulation provides a high degree of confidence for the engineer, limited mainly by the “granularity” of simulation elements (and hence the time to perform the simulation) and, subsequently, manufacturing adherence to the simulated design. Once satisfied with the simulated results, engineering switches to the “real world” and a working prototype is built. This is the most critical phase of product development, since the device is checked and compared against the simulated model and verified that it meets interoperability standards.

Testing High-Speed Serial-Data Buses
Engineers need to confirm that high-speed serial buses are delivering data correctly, and that serial transmission issues aren’t adversely affecting other system elements. The latest standards have faster edge rates and narrower data pulses, creating unique, exacting demands on the verification, debug, and testing processes.

As multi-gigabit data rates become common in digital systems, signal integrity—the quality of the signal necessary for proper operation of an integrated circuit— is becoming a paramount concern for designers. One bad bit in the data stream can dramatically impact the outcome of an instruction or transaction.

Factors that can cause impairments in the transmitted signal quality include:

• Gigabit signal speeds: Ultra-fast transfer rates, low-voltage differential signals, and multi-level signaling are susceptible to signalintegrity issues, differential skew, noise, and analog interference. Serial buses can be implemented as single lanes and as multiplelane architectures for increased data throughput, which adds to overall design complexity.

• Jitter: With high data rates and embedded clocks, modern serial devices can be susceptible to jitter that creates transmission errors and degrades bit-errorrate performance. Jitter, which is the deviation from ideal timing of an event, occurs due to crosstalk, system noise, simultaneous switching outputs, and other regularly occurring interference sources.

• Transmission-line effects: With serial-data technologies, the signal transmitter, transmission line, and receiver constitute a serialdata network. Transmission effects such as reflections and impedance discontinuities can significantly impact signal quality and lead to transmission errors.

• Noise: Noise is any unwanted signal that appears in the sampled data. Noise comes from both external sources, such as the ac power line, and internal sources, such as digital clocks, microprocessors, and switchedmode power supplies.

Higher-speed digital signals with embedded clocks display characteristics that appear more and more analog-like, making design validation and system integration ever more challenging. Demand for precise validation, characterisation, and stress testing under a wide variety of conditions will complicate the challenge—signals tend to become unreliable under even a small amount of distortion or jitter.

Test Processes
To aid engineers, the design and operation of serial data technologies are defined in standards documents, usually the product of an industry committee. Each standard also requires specialised measurements and compliance testing procedures, which add engineering work beyond the already complex design task.

The standards address data signaling and encoding, packetisation, clock embedding, transmission properties, and compliance test procedures. With clear standards and test procedures for highspeed serial technologies, designers can create products that provide off-the-shelf interoperability.

Serial-Data Test Phases
Typical high-speed serial-data test phases include:

• Design verification: Design and test engineers need to ensure that the real-world operation of their designs meets the design simulation and technical performance specifications, and that it’s fully functional. This requires complete characterisation, debugging, and analysis under both realistic and limit stress conditions.

• Characterisation: During the initial testing of a component, designers will characterise performance to determine if the signal behaviours are within specification. A host of precise measurements must be made, often in real time, to determine if the high-speed buses are actually working properly.

• Troubleshooting: Any discovered characterisation or operational issues require engineers to debug and isolate failures or anomaly conditions, such as hardware timing, crosstalk, signal quality, and/or software design problems.

• Compliance test: Ensuring plugand- play compatibility between multiple vendors and products requires confirmation of final designs to industry-specific serial- data standards.

Engineers will often need to fully evaluate performance at both the chip and system level. At gigahertz speeds, there’s greater susceptibility to timing problems in the form of jitter, impedance discontinuities between a transmitter and receiver, or system-level interaction between hardware and software. Comprehensive analysis tools are required at all design phases to provide deeper insight and to fully characterise and isolate marginal design or system effects.

“New Digital World” technologies, founded on advanced processing and high-speed serial transmission, offers numerous opportunities for innovation and growth. However, engineers must be able to manage the implementation risks carefully in order to avoid those dreaded budget and timescale overruns. Ultimately, new techniques and tools for each phase of the development cycle represent the keys to successful implementation.

TREVOR SMITH is EMEA market development manager, oscilloscopes and signal sources, Tektronix

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