Electronic Design

Synthesized Clock Generator Boasts Less Than 1-ps Jitter

The development of digital circuitry can go more smoothly with the use of precise, low-jitter digital clock signals supplied by the CG635 synthesized clock generator. Developed by Stanford Research Systems, it generates single-ended and differential clocks from 1 mHz to 2.05 GHz with jitter below 1 ps rms. Frequency resolution is 0.001 Hz.

Amplitude and offset are continuously adjustable. Standard CMOS, emitter-coupled logic (ECL), pseudo-ECL (PECL), and low-voltage differential signaling (LVDS) also are available. A rear-panel output supplies RS-485 and LVDS levels over twisted pairs. Phase noise for a 622.08-MHz carrier at a 100-Hz offset is less than ­80 dBc/Hz, and the spurious response is better than ­70 dBc.

An optional pseudorandom binary sequence (PRBS) generator offers clock and data outputs for testing serial data channels. Edge transition times are typically 80 ps. Also optional are an ovenized crystal oscillator or rubidium frequency standard to improve frequency stability and reduce aging effects. The unit can be locked to an external 10-MHz timebase.

The CG635 costs $2490. The PRBS option is $550, the ovenized timebase is priced at $650, and the rubidium timebase is $1650.

Stanford Research Systems

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