Creating the complex triggers described in the main article demands a lot of power. A typical tool that contains the necessary power is Agilent Technologies' 16717A state and timing logic-analyzer module. The combination of this hardware and the company's VisiTrigger system makes setup a snap. In addition, predefined terms, such as those provided with the Agilent E2466B Pentium Pro analysis probe, let designers set up real trigger sequences that mimic the P6 family system-bus operation. To show how the flowchart version of a trigger can be turned into an actual logic-analyzer trigger sequence, we'll prepare two triggers on the 16700A logic-analysis system.
Trigger Example 1: Transaction type with address. The software available with the analysis probes predefines many common buses' transaction types. This "trigger on transaction type with a specific memory address" begins by looking for the transaction type "Mem Write" and address "89ABCDEF" to both occur at the same time. The set of signals "REQa#" is used in this software, because the transaction type of the Pentium Pro bus is defined in the "REQa" signals (Fig. A).
Trigger Example 2: Capturing only I/O writes to a specific port. Four-way branching, as well as the use of storage qualification, is demonstrated when a trigger is set up to just capture I/O writes to a certain port. The specifics of the flowchart shown in the main article are easy to map onto the logic-analyzer trigger menu. To provide a clean view of the I/O writes, simply override the storage qualification in each sequence level.
To start, we set the storage qualification to "Nothing." This is done in the "Default Storing" tab of the 16717A trigger menu. It has three choices from which to choose: Nothing, Anything, or Custom. At "Nothing," the sequence will never capture anything unless we override it (Fig. B).
Next, we turn to flowchart level 1, which we translate into sequence level 1. This sequence level is very similar to the one described above. But it moves us to the next level upon detection, instead of triggering. It also includes the action to "Store sample," which overrides the default storing of "Nothing." We can use the action area of the sequencer to increment a counter. Although not completely necessary, this step will act like a "printf"-type statement, helping to count the total number of Port 80 writes that we find (Fig. C).
Sequence level 2 closely mimics the flowchart. The four-way branch in this level was chosen from the "Trigger Functions" area of the menu, and then customized to fulfill the requirements stated in the flowchart (Fig. D).
For this trigger, the four response-detector levels (3, 4, 5, and 6) are identical. Again, they closely follow the flowchart. They must store samples to override default storing, while looking for the response phase. To accomplish this, an if-else structure is used. If anything but a response is found on the clock edge, this sequence will store a sample and continue checking for a response. Each level will track all of the bus action (snoop and error phases) until that response is detected. We continue to the next level based on detection of the response lines doing anything, which is shown as "not nothing" (!= ---) here (Fig. E).
Finally, sequence level 7 needs to be created. This level is not complicated. It simply stores away five states for maintenance. Then, it goes back to the beginning to start the search once again (Fig. F). As you can see, the combination of predefined labels and the insight provided by the flowchart make it relatively easy to translate the flowchart into a trigger definition.
