Multicore Security Processor Handles 40 Gbits/s

Nitrox III block diagram

Cavium Networks lastest security processor, the Nitrox III, handles 40 Gbit/s data streams using a multicore architecture (Fig. 1) with up to 64 Giga Cipher RISC cores and 4 compression engines. Its support for single root I/O virtualization (SR-IOV) is key to distributing the chips power among virtualized hosts. The chip targets a range of applications from 3G and 4G/LTE infrastructure to cloud computing environments.

The chip can handle all major protocols such as IPSEC, SSL, TLS, DTLS and ECC Suite B. Its algorithm support is extensive as well including 256-bit AES. The high end version of the Nitrox III can handle 200K RSA Ops/s and 35K RSA Ops/s for 1024 bit and 2048 bit keys respectively. The bank of compression engines can encrypt or decrypt GZip and LZS at 20 Gbit/s and 10 Gbit/s rates respectively. The random number generator (RNG) is FIPS 140-3 compliant and is designed to handle the latest NIST specification.

The Nitrox III uses a x16 PCI Express Gen 2 interface. It does not require any off-chip memory. Out of band configuration is handled by I²C or serial EEPROM. Power requirements range from 10W to 20W depending upon the number of cores. The various versions of the Nitrox III are pin compatible. They are available in 27mm by 27mm packages.

• ^{Cavium Networks}
• ^{Cavium Networks Nitrox III}