This year marks a transition from 3G to 4G wireless system deployments. Average per-user data rates will rise from 2 Mbits/s (3G) to 50 Mbits/s (4G), with much of the increase delivered by multiple-input multiple-output (MIMO) smart antenna algorithms (see “Multi-Antenna Designs Turn MIMO Testing Into Heavy Work”).
Rising 4G data rates and a rapidly increasing number of mobile users per basestation will require more bandwidth on the fiber-optic cables that connect the remote radio heads (RRHs) at the top of cellular towers and the baseband equipment on the ground (see “High-Gain Wide-Dynamic-Range Dual Mixer Targets 4G Basestation Receivers”). The lower coverage of 4G technology will also drive the greater use of distributed basestations using wave-division-multiplexing to connect distributed radio heads to centralized baseband processors.
Unfortunately, new 10-Gbit/s fiber-optic links cost many hundreds of dollars, driven by the cost of optical transceivers and high-speed serializer-deserializers (SERDES) in FPGAs and ASICs. With newly deployed Long-Term Evolution (LTE) sectors numbering in the low millions, these new optical links represent hundreds of millions of dollars of wireless infrastructure cost.
Many basestation vendors already use FPGAs that interface to optical transceivers in both RRH and baseband equipment, so a compressor for 3G and 4G baseband packets could be easily integrated into FPGAs, reducing the bandwidth on optical links without sacrificing signal quality.
The Role Of CPRI
Fiber-optic cables that connect RRHs and baseband chassis use the Common Packet Radio Interface (CPRI) protocol, downloadable from www.cpri.org. CPRI links carry payload units called antenna-carriers that deliver one carrier received or transmitted using one antenna. With 4G systems using two, four, or even eight antennas per sector and with up to 20-MHz carrier bandwidths, the fastest 4G CPRI links will require 12-Gbit/s SERDES.
One recent announcement by a wireless infrastructure vendor validated the requirement for CPRI compression for its next-generation basestation architecture. But for successful implementations of CPRI compression, the industry should consider the following five questions:
• What is the compression algorithm’s rate-distortion curve using 4G test model signals, where distortion is measured in error-vector magnitude (EVM)? At first glance, CPRI antenna-carrier packets do not offer much opportunity for compression. Antenna-carriers are critically sampled (e.g., a 20-MHz orthogonal frequency-division multiplexing or OFDM carrier is sampled at 30.72 Msamples/s complex, 15 bits per sample) and thus do not exhibit sample-to-sample correlation.
• How much of the signal chain EVM budget shall be allocated to CPRI compression? The rms EVM specification for the entire LTE downlink signal chain is 8% for 64-state quadrature amplitude modulation (64QAM), and it must be allocated to the different components, including CPRI, digital IF combining, crest factor reduction, digital predistortion, RF upconversion, and the power amplifier, in a way that balances OEM cost and performance objectives.
• What is the algorithm’s complexity? With up to eight instantiations of compression and decompression required per sector, the logic complexity of the compression algorithm will add up quickly.
• What is the algorithm’s latency? Wideband CDMA is a wireless technology that’s most sensitive to latency, limiting the roundtrip latency specification in CPRI to 5 μs.
• Is the compression technology proprietary or available to the wireless infrastructure ecosystem?
The figure illustrates the rate-distortion curve for the LTE downlink for one such compression algorithm, Prism IQ from Samplify. At 3.75 effective bits, which translates to 4:1 compression starting from 15 bits, the compression distortion meets the EVM limit of 8% for LTE. It is up to the wireless OEM to determine the allocation of this EVM budget to CPRI compression. At 2:1 compression the EVM is just 0.5%, which is virtually lossless in terms of the system EVM budget.
In terms of complexity, Prism IQ requires 1200 Xilinx slices, 2000 Altera ALMs, or about 100k ASIC gates. Prism IQ’s latency is less than 1.5 µs, well below the 5-µs CPRI latency spec. Prism IQ is available now for FPGA and ASIC implementations to all basestation manufacturers, operators, and chip vendors alike, under reasonable and non-discriminatory (RAND) terms. With such significant 4G infrastructure cost savings enabled by compression, the industry should carefully consider the available options before selecting a CPRI compression solution.