Many electronic systems require one or more negative supply rails, typically implemented alongside corresponding positive rails to form symmetrical power supplies. These negative voltages are essential for proper biasing, signal swing, and device operation in various applications, including gate-driver circuits for EV power electronics. This enables efficient switching of wide-bandgap semiconductors such as gallium-nitride (GaN) FETs and silicon-carbide (SiC) MOSFETs in onboard chargers (OBCs) and traction inverters.

Precision analog front ends (AFEs), including high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), require negative rails to deliver a full dynamic range and linearity in industrial and medical equipment. Rail-to-rail op amps used in many of the same signal chains need negative supply voltages for the same reason. Medical imaging equipment depends on negative voltages for detector bias and signal conditioning.

In data centers, optical transceivers apply negative bias voltages to photodiodes, which take light signals shooting through fiber-optic cables and translate them into electrical signals for servers and switches. The negative bias voltage helps them achieve high-speed response and low-noise operation. In consumer electronics, negative voltages are also used to control pixels and adjust contrast in high-resolution LCD displays.

These negative rails are typically generated using the inverting buck-boost (IBB) topology. In these cases, engineers can use a buck-boost regulator specifically designed for negative-output operation. Alternatively, a standard buck regulator could be reconfigured for inverting operation by rerouting the power stage. The differences between these approaches are outlined in Figure 1, which shows a dedicated IBB solution, and Figure 2, which illustrates a buck regulator configured to output negative voltages.

Since there are tradeoffs with each approach, a practical design example can help illustrate their pros and cons. The process starts with power-stage design considerations based on a set of electrical requirements and then discusses how to develop the small-signal control-to-output transfer function for peak current-mode control operating in continuous conduction mode (CCM). The design requirements, including small-signal linear operation around the steady-state operating point, are in Table 1.

Using the model, a voltage-loop compensator can be developed for the power stage to improve loop stability and transient response. The analysis assumes a peak current-mode controlled converter with internal slope compensation and a high-bandwidth inner current loop, allowing the outer voltage loop to be modeled with a Type-II (two-pole, one-zero) compensator. For devices with internal compensation, designers should follow the recommendations provided in the respective datasheets.

Step-By-Step Process for Power-Stage Design

Here’s the step-by-step procedure for designing the power stage.

1. For an IBB converter, the ideal duty cycle is calculated using the magnitude of the output voltage:

1. The average current through the inductor is determined as:

    2. The peak inductor current can be calculated using the following expression, assuming an AC ripple current of 30% of the average inductor current (represented by 0.3):

where:

    3. The inductor to be selected should have an I RMS rating greater than I_L, and I_SAT rating greater than I_L,peak. The inductance required is determined as:

For buck-converter ICs configured in IBB mode with a duty cycle greater than 50%, the selected inductance must exceed the minimum required inductance L_min, as specified in the respective product datasheet. The example formula from the LT8624S is as follows:

When applying the L_min formula for the IBB configuration, replace V_IN with V_IN + |V_OUT|, and use the duty cycle D, calculated in Step 1. The resulting formula is:

    4. The right-half-plane (RHP) zero is determined by the following equation:

Since the V_OUT is negative, the absolute value of the same is considered.

1. The target crossover frequency, f_cr, is at a range of 0.1 × f_rhp to 0.3 × f_rhp. Selecting f_cr = 0.3 × f_rhp Hz.
2. Considering a step load current, I_STEP = 0.5 × I_OUT for a 3% V_OUT ripple (ΔV_OUT = 0.03 × V_OUT), the output capacitance is calculated as:

Note that the C_OUT value calculated is derated to V_OUT.

1. The slope compensation, S_E, is determined from Equation 7, which is the denominator, that is 2.5 × f_SW A/s.
2. The current-sense resistance, R_i, can be approximated by:

Generally, the slope and the current-sense information aren’t made directly available in the datasheet.

1. Evaluate the inductor current slope S_N as:

    2. The power stage output-to-control transfer function can be calculated with:

where:

The value, R_C, is the ESR of the output capacitor in Ω.

The parameters of the power supply are shown in Table 2.

Completing the Buck-Boost Converter with a Compensator

Figure 3 represents a two-pole, one-zero voltage Type-II voltage-loop compensator. The transfer function of the component can be calculated as:

The combination of the control to output transfer function and the output voltage feedback provides insight into designing the compensator transfer function. From there, you can follow these step-by-step guidelines:

1. The additional gain required for the loop transfer function to obtain the required bandwidth:

where:

    2. The phase shift of the power-stage transfer function is represented:

    3. For a buck-boost converter, a good phase margin is above 45°. Selecting a PM of 60°, the phase boost required is:

    4. The factor k is evaluated as:

    5. The compensator pole ω_pc and compensator zero ω_zc are obtained as:

    6. The integrator gain is obtained as:

    7. The components for the above compensator are designed as:

Table 3 shows the compensator designed for the power stage.

Simulating the Circuit and Testing Its Performance

The simulation of the IBB stage, configured with the parameters derived in Table 3, is shown in Figure 4.

At a crossover frequency of 46.269 kHz, the loop exhibits a gain margin (GM) of 8.90 dB and a PM of 59.07°; GM is expected to be greater than 10 dB. This can be improved by tuning the compensator pole. In this design, transient response was prioritized over gain margin, resulting in a measured GM of 8.9 dB, which is acceptable for the intended operating range.

During the load step, the transient waveform exhibits an output-voltage excursion of roughly 2.88%, indicating the converter’s dynamic response characteristics (Fig. 5).

Given all that, it’s evident that the selection of the inductor, L, directly influences the location of the RHP zero and, consequently, limits the maximum achievable crossover frequency of the IBB converter. The choice of output capacitance, C_OUT, not only determines the output-voltage excursion during load transients, but together with its equivalent series resistance (ESR) and inductor L also shapes the dominant power-stage pole.

These parameters collectively dictate the required loop gain and phase boost during compensator design, ultimately determining the resulting phase margin of the system.

This checklist outlines the essential design requirements:

• High RHP zero for adequate bandwidth (via inductance selection).
• Phase margin (PM) > 45°.
• GM ≥ 10 dB is recommended; however, slightly lower GM may be acceptable when transient performance is prioritized.
• Output voltage deviation ≤ 3% during load transients.

Conclusion

This step-by-step guide gives engineers a systematic approach to compensator design for IBB converters. By deriving the small-signal power-stage model and explicitly accounting for the RHP zero, designers can select an appropriate loop bandwidth and compensation network. The LTspice simulations can be used to confirm that the proposed method achieves stable operation and fast transient response, making it suitable for a wide range of negative-rail-generation applications.

References

Basso, Christophe P. Switch-Mode Power Supplies, Second Edition. McGraw-Hill Professional, February 2008.

Lamp, Erik. “Fast-Transient Negative Voltage Rail for Noise-Sensitive Applications.” Analog Devices, July 2024.

Lamp, Erik and Randyco Prasetyo. “Generating Negative Voltages from a Positive Voltage Supply: Market Requirements and Solutions.” Analog Devices, September 2024.

Mitra, Dipankar. “How to Use the MAX17501 and MAX17502 for Negative Output Voltage Applications.” Analog Devices, April 2014.

Nelson, Carl. “AN19—LT1070 Design Manual.” Linear Technology, June 1986.

Ridley, Raymond B. “A New Small-Signal Model for Current-Mode Control.” Ridley Engineering, 1999.