When I needed to create a simple tool to generate a long, event-triggered pulse, I started with a classic one-shot and a really large capacitor. This worked "pretty good," owing to the classic nature of the problem. There seemed to be no enthusiasm for using a small controller to provide the one-shot function, though. Nonetheless, there may be several advantages to doing so.
Generally, larger caps have a wide initial tolerance and variation over temperature, but a controller-based application can take advantage of Microchip’s 10F204—in an SOT-23 package—as well as a smaller NPO capacitor, with its nearly flat temperature variation and a 1% resistor to set the delay. This saves the expense and footprint of larger, more expensive caps that otherwise may be needed.
This implementation codes the 10F204 with a delay translator that takes a calculated delay, determined by the small RC components, and generates a proportionally long output pulse. The external RC values in the circuit in Figure 1 depend on how many basic, 5-µs steps are required to trip the 10F204’s on-chip comparator, when it’s referred to its internal 0.6-V reference. Sequenced processes maintain the external capacitor in a discharged state and float the input, monitoring the comparator output to determine the time to charge above the reference. These external components are evaluated at power-up, when the controller is re-enabled and during the first 1-ms timing step following each trigger.
The remaining coded processes provide the enable, retrigger qualification, multiplier, and loop indexing within a branch-equalized 1-ms loop.
Equation 1 calculates the values of R and C needed to create the desired delay described in Equations 2 and 3.
Loops = ABS(INT(R*C* (ln(1-VTRIP/VCHARGING))/5 µs)) (1)
VTRIP is the reference comparator voltage. VCHARGING is the voltage source used to charge the external capacitor and should be a stable value greater than VTRIP. In this example, it’s the same as the regulated VDD used to power the controller.
Several operational parameters are needed to define this code-based application. These include:
1. Selection of low-to-high and high-to-low trigger edge sense:
- 0 configures the TMR0 clock input edge for low-to-high trigger
- 1 configures the TMR0 clock input edge for high-to-low trigger
2. Selection of either single-trigger or retrigger operation:
- 0 configures for single-trigger operation (triggers during active and output are ignored),
- 1 configures for retrigger operation (any trigger reinitializes the delay).
3. Defining the 8-bit loop multiplier used in the delay computation (see below).
4. An internal state flag, capsen, configured to determine how the detected component-based loop count is processed:
- state flag = 0 uses the calculated Loop count value directly and is constrained to a value of 1 to 127
- state flag = 1 subtracts the calculated Loop value from 256, resulting in a value of 255 to 128
Based on these options, the maximum delay is provided when the state flag is configured with a 1. This gives:
state flag = 1: delay = (255 - Loops) * multiplier * 1 ms (2)
And for the state flag = 0:
state flag = 0 : delay = Loops * multiplier * 1 ms (3)
Figure 2 shows the resulting delays for Loops values obtained in Equation 1. The longer delays occur when the state flag is set at 1, and the shorter delays reflect the state flag set to 0. Resistance, R, is limited to 10 k Ω and constrained to 1 k Ω in this analysis.
For a specific multiplier, the range of delays is constrained by the external components. Varying both the R and C allows for a significant variation in delay. The trigger pulse width is a minimum of 2 µs, while the trigger-to-output-active delay is a minimum of 2 µs and a maximum of 12 µs.
The accuracy (independent of RC component variation) is dominated by the tolerance of the internal instruction period. This is defined as 1% over a narrow voltage and temperature range. Tolerances of pin 1’s output-low voltage (used to discharge the capacitor), the internal comparator, and 0.6-V reference also will impact initial accuracy. Changes in delay over time and temperature depend on all component variations. The value of the multiplier is a code-based constant and will not vary.
Click here to get the assembly code for this example application and a spreadsheet, with instructions, to help calculate voltage, multiplier, and component values.
To use the spreadsheet to calculate voltage, multiplier, and component values for the controller-based one-shot:
- Set the Charging voltage, Vc, to your regulated supply or reference voltage.
- Set the Trip voltage Vt to .6.
- Set the Multiplier to 1.
For reference only, set the desired delay, enter state flag 1 or 0 based on this number.
Set the cap value in nF to any value.
Go to the table:
In the first column of the table’s top row, I have copied the cap value entered above, converted to Farads. The remaining entries, along this row, have standard cap values, in F, and may be re-entered with what ever values you would like.
The left column of the table has resistor values from 1000 to 10,000. 10,000 is a limit imposed by the controller. The column is a linear list. You may change this column to identify standard values for 2%, 1%, … 0.1%.
The table uses these R and C values and the Multiplier value, entered above, to generate the delay values using Eq. 1, 2, and 3, referenced in the article.
You may want to do a little math to get you into the "Ball Park."
Settle on values for R, C, and the Multiplier.
You may want to select a set of values which rely more on the Multiplier.
The multiplier is a coded value and does contribute to timing variation.
It is best to accommodate RC values that produce Loops values (using Eq. 1), that are smaller rather than larger. Migrate the possible R and C values to the spreadsheet cells at the top of the form and read the Loops value directly.
The variation in the cap’s discharge voltage will have less effect on the calculated Loops count. Also, to reduce component sensitivity with small cap values, you want to constrain the R and C values to the linear slope portion of the (1-e'-t/RC) curve generated during component evaluation.
Select values that demonstrate delay stability in the table. This will be seen in the table with adjacent table values that don’t change.