Hardware designers are feeling the pressure from designs with continually accelerating memory or SERDES protocol links, while facing shrinking margins and unrelenting cost constraints. I believe we have finally reached the point where “sign off” verification is a requirement on these interfaces before going to your first layout.
What is signoff verification? Reviewing your board to see if you match the IC vendor’s product-development guide? Simulating every high-speed net on the board with IBIS models? What about power integrity? IR drop? Decoupling analysis?
As a tool provider, I would say signoff verification encompasses all of the above… but to what extent? You could try and do everything with full 3D extraction, adding detailed package models… does your watch have a third hand for days of the week? Maybe you have had success just doing manual inspection of the layout based on the platform IC vendor’s guidelines (e.g., length matching, impedance, and decoupling requirements).
At Mentor, we sponsor the annual Technology Leadership Awards and get hundreds of boards submitted from around the world, so we get a pretty darn good idea of what’s going on out there. Have you seen how dense some of these boards are becoming? Manual inspection is crazy difficult—error-prone at best.
What’s Your Comfort Level?
How do you triage the board and find out what nets need your attention? Maybe the first question should be, what type of verification are you even comfortable with? Are you a hardware designer? Okay, then you’re comfortable with waveforms, setup-and-hold times, and differential impedance. But maybe you’re not a DDR4 protocol expert and are unfamiliar with write leveling or slew-rate derating tables. Or maybe you understand those, but aren’t comfortable with defining ports to a 3D EM solver. My guess for you: rules and waveforms are both okay.
Are you a PCB designer—uncomfortable with waveforms, but totally accustomed to using design-rule checks for clearance, pad size, length matching, etc.? Frequency-domain analysis, maybe not. Rules for sure, and maybe some waveforms. If you’re a signal-integrity expert… well, you could be writing this article, so I count you “all in” for both rules and waveforms—maybe even preferring the latter. Bottom line: Your level of verification needs to map to your understanding of the results. Don’t ask for results you won’t be able to respond to.
Let the Problem Be Your Guide
What about choosing rules or waveforms based on the problem itself? Let’s start with electromagnetic interference (EMI). Those problems are typically hard to find and usually only after you have the board fully stuffed and in the anechoic chamber. Simulations are very hard to do, and simply not practical on a system level. Predicting far field is compute-intensive and only as accurate as the 3D extraction, enclosure modeling, and defining the stimulus to drive the whole board to radiate as it would when in operation.
However, we can find the major causes with rules that search for the creation of unwanted antennas (e.g.. high-speed nets with breaks in their return paths) pretty quickly. We can even do it on partially routed boards, letting the designer know as soon as he has created a possible problem, before too much “un-routing” needs to happen to correct it.
Next up: Power integrity (PI). Rules like decoupling capacitor placement (distance to IC power pins) run very fast and will indicate which capacitors are poorly placed or mounted, but won’t guarantee performance over frequency. For dc drop, net width rules will help with trace-routed power, but won’t handle the multipath problem in modern boards with heavily perforated planes that require some kind of mesh-based simulation. Good news here: Setup is easy and IR drop reports are easy to understand. A PCB designer knows exactly what do to solve current density problems: add more metal.
How about impedance of the entire Power Delivery Network (PDN) over frequency? Today’s low-voltage, high-current, high-frequency devices are more dependent on the response of the power planes and the cavities between them for power delivery. This is definitely time for decoupling simulations, looking for response across frequency, resonances, noisy versus quiet locations on the board, and more. Setup is a bit more difficult than IR drop, including finding accurate capacitor models with correct mounted ESL (i.e., don’t trust something from a data sheet that came from measuring the device on a different stack-up than yours).
What about signal integrity (SI)? Rules and waveforms both have a role here. Some of the same problems that can recreate EMI can create poor signal quality with loss and reflections. Reference plane changes without proper bypassing—good for a rule, but hard to simulate without 3D extraction and solve for the areas where the signal changes reference. High-speed nets across gaps in the return path have the same issues; rules are perfect here.
How about length matching on a DDR data to bus strobe? Good for a rule, but it won’t assure there are no issues from JEDEC de-rating based on varying slew rates. Simulation is needed for that. Full verification of a DDR interface needs to be a combination of timing and SI simulation to be sign-off quality. Things like write leveling, on die terminations, etc., drive this.
What about PCI Express or Ethernet? I think this depends on speed. Rules are probably okay at slower speeds. Most ICs have enough flexibility in settings for pre-emphasis and equalization that can overcome channel issues. FR4 loss isn’t a huge factor at slower speeds. Stay away from phase differences and reference plane changes, and you are probably good to go.
Now jump to 12 or 20+ Gps—where everything matters—and I mean everything. Via transitions need 3D extraction and 3D solvers; materials characteristics are needed for surface roughness and dielectric loss; exact pad stack data; breakout area details; and more. Time- and/or frequency-domain simulations are no longer an option. These speeds are like arterial bleeding—pull out the heavyweight solvers, decompose the channel, and simulate. Get to these first.
Safety? A good example here is high-voltage net creepage and clearance rules. There’s no way to simulate this; it’s a basic distance along the dielectric surface (not point-to-point), and when the designer goes below it, this could result in a current path (breakdown) to ground or reference. The manual approach is today’s standard, but tools are available that can do this today. And because these tools run on a computer, the rules can be run often, preventing major rerouting late in a layout cycle.
So, there’s no easy answer. Most engineers are comfortable with such a scenario, but it’s their job to find answers. Rules and waveforms are both available to help find those answers. If and when to use them varies, and it depends on user comfort and the problem at hand. I hope this short dialogue stimulates some conversations, but the days of using nothing and getting first pass success are behind us.
To learn more about electrical design rule checking, click here.