Seoul, Korea, and Tokyo, Japan: Samsung Electronics and Toshiba have announced plans to jointly develop double-data-rate (DDR) NAND flash memory with a 400-Mbit/s interface and a toggle DDR 2.0 specification. Both companies say they will support a standard industry specification to enable broad-scale acceptance of this new high-speed technology.
The current toggle DDR 1.0 specification applies a DDR interface to conventional single-data rate (SDR) NAND architecture. The resulting NAND chip has a 133-Mbit/s interface. Samsung and Toshiba will focus on ensuring a 400-Mbit/s interface for the toggle DDR 2.0 specification, which provides a threefold increase over toggle DDR 1.0 and a tenfold increase over 40-Mbit/s SDR NAND in widespread use today.
The consequence of an industry-wide adoption of the high-speed specification would facilitate faster acceptance of toggle DDR memory with hardware engineers and application designers. Last month, each company started participating in standardization efforts for the new technology through the JEDEC Solid State Technology Association.