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The introduction of double-data-rate (DDR) memory has afforded a quantum leap in performance for commercially available desktop and portable computers. That's a step much warranted by the multigigahertz processor speeds found on today's motherboards.
With a 2.6-GHz CPU, typical 100-Mbit/s SDRAM would be a throughput bottleneck. Brute-force speed increases in standard SDRAM create power-dissipation, noise-margin, transmission-line, and cost problems. Adding DDR memory doubles the data-transfer rate without doubling the clock rate, avoiding pc-board design and layout complexity. However, it requires that the DDR regulators have tighter dc regulation, higher currents, and close tracking for both the VTT (termination supply voltage) and VDD (memory bus supply voltage) regulators.
For the PC2100 device discussed in the article, a new approach to data transmission and line termination was adopted so that the data lines can switch at twice their previous speeds over the same pc-board traces. The DDR266 device employed has a clock frequency of 133 MHz and a peak data transfer of 266 Mbits/s. That's 2.1 Gbytes/s (PC2100) for a 64-bit wide bus over the same pc-board traces of the PC133 (266 × 8 = 2100).
Power considerations when moving from single-data-rate (SDR) to DDR memory are discussed. Newer DDR2-type memories should bring considerable power savings over the current DDR1 version due to lower-voltage rails.
Other key considerations are dc-dc converter compliance with DDR power and bus accuracy, along with meeting timing and sequencing guidelines. The regulator comes into play here.
| HIGHLIGHTS: | |
| Noise-Margin Calculations | Termination Resistors for DDR are selected based on factors such as worst-case drive source resistance (RON) and length of pc-board trace. |
| DDR Power Considerations | Moving from single-data-rate (SDR) memory to DDR brings new power requirements to VDOQ as well as the I/Os. DDR2-type memory (VDOQ = 1.8 V) consumes 30% less power than DDR1 (VDOQ = 2.5 V) versions. |
| Dual Channels | The newer dual-channel data-bus architecture (DDR2) doubles the number of data bits by using two 64-bit data buses. The bus basically doubles the active current associated with DDR DRAMs. |
| Integrated DDR Controllers | To take full advantage of the DDR memory, the dc-dc converters must comply with the DDR power and bus-accuracy requirements. IAPC (instantly available PC) specifications for timing and sequencing further complicate matters. Thus a regulator like the SC2616, which is detailed in the article, is crucial in this case. |
Full article begins on Page 2
Tighter dc regulation, higher output currents, and close tracking of the memory-bus and termination supply voltages make for happy memories. The introduction of double-data-rate (DDR) memory has afforded a quantum leap in performance for commercially available desktop and portable computers.
That's a step much warranted by the multigigahertz processor speeds found on today's motherboards.
With a CPU running at 2.6 GHz, the typical synchronous dynamic random-access-memory (SDRAM) data rate of 100 Mbits/s would be a throughput bottleneck. Moreover, pushing standard SDRAM speeds through a brute force increase in memory clock speed throws up roadblocks such as power dissipation, noise margin, transmission-line limitations, and most importantly, cost. In contrast, DDR memory doubles the data-transfer rate without doubling the clock rate. This avoids a corresponding rise in pc-board design and layout complexity, which is common among high-speed motherboards.
However, adding the DDR data bus means more stringent requirements for the DDR regulator—tighter dc regulation, higher currents, and close tracking for VDD (memory bus supply voltage) and VTT (termination supply voltage) regulators. The VTT must track VDDQ/2 to within ±40 mV to ensure symmetry of the error band around the receiver's logic threshold. DDR's new stub series-termination-logic (SSTL) topology improves noise immunity, increases power-supply rejection, and reduces power dissipation (for comparable speeds) due to a lower-voltage rail. JEDEC Standards JESD8-9A (for SSTL_2) and JESD 8-15 (for SSTL_18) define the VDDQ, VTT, and VREF, as well as driver/receiver specifications to meet noise margins for VDDQ = 2.5 V (DDR1) and VDDQ = 1.8 V (DDR2), respectively.
While the DDR SDRAM provides true source-synchronous data capture at twice the data rate, the address lines, command-control interface, memory arrays, and refresh requirements didn't change from the corresponding single-data-rate (SDR) SDRAM. Thus, the fundamental differences are found in the data-bus interface.
A DDR266 device with a clock frequency of 133 MHz has a peak data transfer of 266 Mbits/s. That's 2.1 Gbytes/s (PC2100) for a 64-bit (8-byte) wide bus over the same PC133 pc-board traces (266 × 8 = 2100). This is accomplished by the DDR SDRAM utilizing a 2n-prefetch architecture, where the external data bus is twice the speed of the internal data bus. Data is captured once at the rising edge and once at the falling edge of the clock. Figure 1 shows the data-transfer path and termination configuration for a typical motherboard transferring data to and from DDR memory.
Because the data lines must switch at twice their previous speeds over the same pc-board traces, a new approach to data transmission and line termination (SSTL2) was adopted. While the address and control lines are shown with termination resistors to the VTT island, this termination generally isn't employed for PC2100 systems. That's because the command and address buses are still clocked at the 133-MHz rate. In contrast, the SDR DRAM uses single-ended LVTTL or LVCMOS signaling, which suffers from wide voltage swings, and asymmetry of logic thresholds due to temperature, voltage, and component tolerances. Figure 2 shows the different voltages and termination configuration for DDR and SDR signaling.
The termination resistors for DDR are selected based on several factors, including the worst-case driver source resistance (RON), length of pc-board trace, number of drops along the data bus, and environmental concerns like temperature drift. There are general industry-adopted values for the PC2100 platform. They range from 10 to 33 Ω for the series resistor and between 25 and 56 Ω for the VTT pull-up resistor. Exact values for any DDR system should be verified with either a proven design or full simulation and signal-integrity (SI) analysis.
NOISE-MARGIN CALCULATION Referring to Figure 2a, the noise margin at the receiver under worst-case conditions, assuming driver output resistance RON = 21 Ω for a DDR2 (VDDQ = 1.8 V), is calculated (per JEDEC Standard for SSTL-18) as follows:Assume RS = 20 Ω, RT = 25 Ω and VDDQ(min) = 1.7 V
VREF(min) = 0.49 × VDDQ(min) = 833 mV
VTT = VREF(min) + 40 mV = 873 mV
VIN = VTT(RON + RS)/(RON + RS + RT)
= 873 mV × (41 Ω/66 Ω) = 542 mV
VREF(min) − VIN = 833 mV − 542 mV
= 291 mV
From the JEDEC spec, VIH(ac) = VREF + 250 mV, and VIL(ac) = VREF − 250 mV. Thus, the receiver sees an input of 291 mV and only requires VIN(ac)min of 250 mV, yielding a noise margin of 41 mV. An SSTL-18 driver meeting these conditions while driving low would have an IOL and VOL of:
IOL = (VTT − VIN)/RT
= (873 mV − 542 mV)/25 Ω
= 13.24 mA (driver current capability must be higher than this value for the given driver RON)
VOL = VIN − IOL × RS
= 542 mV − 13.24 mA × 20 Ω
= 277.2 mV
A similar calculation can be done when the receiver is driven high.
DDR POWER CONSIDERATIONS The move from SDR to DDR memory technology brought new power requirements to both VDDQ and the I/Os. Transitioning from DDR1 to DDR2 will further reduce voltage, but the data-bus signaling is expected to retain its basic characteristics. Due to lower-voltage rails, DDR2 devices will consume about 30% less power than DDR1 during the volume production of a given density for the same speed grade. So for a 512-Mbit device, a DDR1-266 power equals DDR2-533 power (twice the data speed, using the same overall power). For comparable speeds, there would be a big difference. For instance, DDR2-400 devices will consume about 30% to 40% less power than a DDR1-400 device.According to memory manufacturer Micron Technology, early production of DDR2 devices may provide somewhat less of a power savings. But once a particular density is in high-volume production, the large delta should be realized. For termination power considerations, DDR2 allows the use of DDR1-style SSTL termination.
A detailed power calculation must consider many variables, such as percentage of access time versus standby time, access types, and separate treatment of "read" and "write" cycles. A worst-case power estimate for the VDDQ and VTT currents in a typical desktop application can give us a good start:
Four DDR266 DIMMs with two ranks/DIMM (both sides of the DIMM are populated) and only one fully active DIMM (i.e., data bus running at maximum speed, a worst-case condition IDD7 with seven ranks in standby) are used. I/O current for the active rank must be included—8 devices × 9 I/Os (DQS must be included):
Total current for the active rank:
(1 rank = 8 components × 8 bits for a 64-bit bus; 1 component has four internal banks of memory)
IACT = Number of active ranks × components × IDD7
IACT(total) = 1 × 9 × IDD7 = 3.6 A, since IDD7(worst case) = 450 mA. (Although the Micron 256-Mbit DDR data sheet lists 380 mA for a maximum IDD7, Micron uses 450 mA for an absolute worst-case number across all DDR densities.)
IIO = Number of devices-per-rank active × number of I/Os per device × I/O current
IIO = 8 × 9 × 16.8 mA = 1.2 A (Note that much of the I/O power is dissipated in the termination.)
The standby current for the other seven ranks, using IDD3N = 50 mA (from the Micron 256-Mbit DDR data sheet):
ISTBY(total) = 7 × 8 × 50 mA = 2.8 A
Thus, for a four-DIMM, dual-rank device, the VDDQ current is:
ITOTAL = IACT + IIO + ISTBY = 3.6 A + 1.2 A + 2.8 A = 7.6 A for four DIMMs of DDR266 memory
The termination voltage, VTT, must be able to sink and source a worst-case current of:
Number of lines × driver current = \[(8 × 8) + 8 (control lines)\] × 16.8 mA = 80 × 16.8 mA = 1.2 A
As noted above, when the VTT supply is in the "sink" mode, the VDDQ supply must source this current, in addition to the previous activate and standby currents. VTT's worst-case current assumes that all of the bits are staying at "0" or "1" for an extended period of time—an unlikely event.
The VDD bus must be "alive" and able to supply current during the motherboard "suspend-to-RAM" mode, S3. This is the current supplied during the DRAM's "self-refresh" cycle. Although VTT power is no longer required while in S3, the DDR memories require VREF to be maintained as a reference for the "self-refresh" cycle. For a four-DIMM DDR266 as discussed above, it is:
IVDDQ = 4 DIMMS × 8 components × 2 ranks × 6 mA (IDD6 from Micron's 256-Mbit DDR data sheet lists 4 mA, but it uses 6 mA for an absolute worst-case number across all DDR densities)
IVDDQ = 4 × 8 × 2 × 6 mA = 0.384 A (95% less than the active current!)
Note that servers generally use x4 devices (instead of x8 for desktops), which roughly doubles the active and standby currents for each rank of memory. In both servers and desktops, modules with error-correction code support are available. If employed, IDD support for an additional x8 or two x4 DDR devices would be necessary. On the other hand, portable computers significantly reduce the DRAM power consumption by using x16 DDR. A detailed DDR SDRAM memory system power calculator can be obtained at www.micron.com/products/category.jsp?path=/DRAM&edID=17594.
DUAL CHANNELS The newer, dual-channel data-bus architecture doubles the number of data bits by using two 64-bit data buses. This widely adopted bus basically doubles the active current associated with the DDR DRAMs. The theoretical maximum for the VTT current increases due to a higher termination load:IVTT = (128 + 1 6) × 16.8 mA = 2.4 A
But the average worst-case current doesn't increase significantly, as it's so unlikely that both channels' I/Os will be stuck driving a one or a zero. Intel specifies this current at 1.8 A.
The VDD bus is also implemented to power the graphic memory control hub (GMCH) DDR inside of the chip set, as well as the 2.5- to 1.5-V linear regulator for the adaptive graphics processor (AGP). The exact current specifications tend to vary from one chip set and motherboard to the next. However, for the Intel Springdale chip set, the VDD bus must be able to supply 19.5 A in S0 (active) and 650 mA in S3 (suspend-to-RAM) mode.
INTEGRATED DDR CONTROLLERS To take full advantage of the DDR memory, the dc-dc converters must comply with the DDR power and bus-accuracy requirements. This is further complicated by a myriad of timing and sequencing guidelines set forth by the instantly available PC (IAPC) specifications. Individual motherboard and chip-set manufacturers often impose unique demands on the controller. Motherboard signals S0, S3, and S5 govern the behavior of the DDR and VTT bus. The regulator is responsible for 20 A of current for the VDDQ (per the latest Intel specs) during S0, or "motherboard-active" state. It must make a smooth transition to and from the S3 or "suspend-to-RAM" state with minimal dc and ac deviations on the VDD bus.In some implementations, the chip set will continue to draw current from the VDD bus for several milliseconds after the S3 has been asserted. The VDD bus must be able to hold the dc accuracy for that duration. Any "drop out" can be catastrophic, as that voltage is also used to retain data and refresh the DDR DRAM.
One example of such a DDR regulator and controller is the SC2616 "three-in-one" DDR controller. It's designed for the latest Intel and AMD motherboards using DDR1 or DDR2 standards. High-current synchronous gate drives are needed to ensure high-output-current capability for the switcher, while the internal VTT regulator must be able to sink and source 1.8 A using the pc board as a heatsink. The DDR controller must also adhere to Advanced Configuration and Power Interface (ACPI) timing and sequencing specifications.
Figure 3 shows a typical connection and the internal block diagram of the SC2616 DDR controller. A MOSFET, with source and drain reversed, is placed in series with the top MOSFET to prevent back-feeding the input supply during "suspend-to-RAM" mode via the top MOSFET body diode.
Power for the VDD bus is supplied from a switching buck converter, stepping down the 5-V input supply to 2.5 V. During S3, as the current is reduced, the 5-VSTBY supply provides the IDDQSTBY current via a linear regulator. When transitioning from S3 to S0, VDDQSTBY proceeds the VDDQ switcher. Thus, the synchronous MOSFET must stay "off" until the switcher takes full control of the output VDD bus to prevent current reversal in the output inductor.
Note that upon assertion of the S3 signal, the VDDQ switcher won't relinquish the bus until the input Silverbox rails drop below undervoltage lockout. This allows sufficient time for the chip-set current to diminish, maintaining the required VDDQ voltage accuracy.
The SC2616's high-speed error amplifier responds to bus transients in less than one pulse-width modulation (PWM) clock cycle. The VDD and VTT rails must be bypassed with low-ESR capacitors near the DIMMs, while the electrolytic capacitors near the dc-dc converter supply the averaged currents. Each bit must also be bypassed with a local ceramic capacitor to provide the fast burst of currents (3 A/ns).
The internal logic and latches of the SC2616 ensure reliable sequencing under all motherboard states, while three different internal thermal-shutdown circuits enable safe operation. The SC2616 reduces the overall solution cost by integrating three regulators in one low-pin-count MLP, with a copper pad for direct heatsinking to the pc board. Figure 4 shows the SC2616 timing diagram and the VDDQ, VDDQSTBY (during S3), and VTT voltages in compliance with the defined S0, S3, and S5 motherboard signals.
Other flavors of the SC2616 are available, such as the SC2614 for Intel-specific motherboards, using the Intel "glue chip" for the BF_CUT signal. The SC2615 and SC2617 controllers, which use a 3.3-V input supply, are tailored toward lower-current DDR1 or DDR2 applications, and come in an MLP package.
Recommended Reading:
Calculating DDR Memory System Power, Technical Note TN-46-03, Micron Technology.
General DDR SDRAM Functionality, Technical Note TN-46-05, Micron Technology.
JEDEC Standard SSTL_2, Dec. 2000, and JEDEC Standard SSTL_18, Oct. 2002.
Special thanks go to Scott Schaefer, applications engineering manager, Micron Technology, for his valuable contributions to this article.