Electronic Design

Designers Must Take Care When Powering High-Speed CMOS

Lower core voltages and higher speeds add up to nasty load transients that place huge demands on power-supply circuits.

DESIGN VIEW is the summary of the complete DESIGN SOLUTION contributed article, which begins on Page 2.

The frenetic pace of advances made in semiconductor process technologies inevitably increases the speed and density of IC devices. Many of these devices, such as DSP-based communication and digital TV ICs, are being designed into systems that traditionally employed lower-performance, dedicated peripheral devices. Designers, however, need to treat the power requirements of these high-performance devices with care.

Because power circuits can be challenging and time-consuming to design, many engineers opt for off-the-shelf dc-dc converter modules. This choice reduces risk and effort, but it may cost more and come up short on performance. For this reason, an in-depth cost/benefit analysis often highlights the advantages of a discrete converter design based on a commercially available step-down (buck) converter IC.

The load response, frequency, power capability, and other specifications of these discrete designs can be more finely controlled to meet critical design criteria. By following 10 key design tips, designers can achieve excellent results in dc-dc power-converter designs for high-performance CMOS ICs. The 10 tips, discussed in detail, are:

  1. Plan your power section first.
  2. Give each high-power device its own converter.
  3. Isolate power and ground sections.
  4. Don't overestimate the regulator's load response capabilities.
  5. Provide proper bypass capacitors, large and small.
  6. Give careful thought to capacitance values and ESR.
  7. Don't forget the input.
  8. Remember Ohm's Law.
  9. Understand that capacitors differ.
  10. Measure the noise.
Plan Your Power Section When designing a high-performance circuit board, consider the power section at the very beginning. Calculate the maximum power requirements needed, and then choose the regulator design type..
Each High-Power Device Gets Its Own Converter By providing a separate power converter for each high-power IC, the converter can be placed next to the device. This will reduce peak transients and the resulting EMI.
Isolate Power And Ground Providing a separate ground path for the digital currents lowers the ground noise (a.k.a. bounce) presented to analog circuitry.
Don't Overestimate The Regulator's Load Response Capabilities Be wary of your power regulator's ability to accommodate extreme changes in current demands. The current peak may be within the regulator's capability, but the specific regulator may not react fast enough to load changes.
Capacitance Values, ESR A large external capacitance with a low equivalent series resistance (ESR) is needed to minimize peak deviation. But because this combo can cause instability, the low- and high-capacitance values must be carefully selected.

Full article begins on Page 2

The frenetic pace of advances made in semiconductor process technologies inevitably increases the speed and density of IC devices. Many of these high-speed devices, such as DSP-based communication and digital TV ICs, are being designed into systems that traditionally employed lower-performance, dedicated peripheral devices. Designers, however, need to treat the power requirements of these high-performance devices with care. For example, many leading-edge processes use a dual-voltage scheme, where the core runs at a lower voltage than the I/O. The low internal core voltage enables fast transitions, and thus higher-frequency operation. The higher-voltage I/O simplifies device interfacing.

These low-voltage circuit cores must be biased meticulously, because even a small voltage drop can mean tolerance violations and potential circuit failure. When CMOS devices change from idle to high-speed mode, the current required to maintain the bias could increase dramatically. Therefore, the circuitry used to power these devices must be able to respond to sudden demands for high current.

Because power circuits can be challenging and time-consuming to design, many engineers opt for off-the-shelf dc-dc converter modules. Though use of regulator modules can reduce design efforts, one should thoroughly think it through before making the choice. Modules cost more and may come up short on key performance specifications. Power module manufacturers may use "specmanship" to highlight product features. Few report details about some important technical parameters, such as load-transient capability or ripple, under real operating conditions.

For this reason, an in-depth cost/benefit analysis often highlights the advantages of a discrete converter design based on a commercially available step-down (buck) converter IC. The load response, frequency, power capability, and other specifications of these discrete designs can be more finely controlled to meet critical design criteria. Moreover, discrete designs are often half the price of modules. By following 10 key design tips, designers can achieve excellent results in dc-dc power-converter designs for high-performance CMOS ICs.

When designing a high-performance circuit board, consider the power section first. Think of it as the foundation upon which all else is built. After the major system components are selected, add up the total maximum current needed to get an idea of the total power required. Then add some extra power for good measure. If you use the maximum requirements for all devices, little additional margin is necessary. You must also understand the system's power-efficiency requirement, and may need to consider meeting evolving energy-efficiency programs.

Once power requirements are known, you can choose a regulator design type. Linear regulators are simpler and faster to design with than switching regulators, so they are tempting. But with high-power circuits, linear regulators may dissipate too much power. This could result in the need for fans and other costly additions. On the other hand, switching power regulators, such as the buck regulator in Figure 1, are often a better choice for delivering core voltages to high-performance devices.

The classic switching buck regulator operates in two phases. In phase one, the high-side switch is on, and the switch transfers energy to the coil. During the second phase, the high-side switch turns off, the low-side switch turns on, and the coil field collapses as its current is drained. The error amplifier compares the output voltage to an internal reference, which feeds the difference term into the pulse-width-modulation (PWM) block to appropriately adjust the duty cycle.

Regulator control loops in dc-dc converters have two basic topologies: voltage mode and current mode. A current-mode controller has a second loop that senses the peak current into the power switches and keeps it constant on a pulse-by-pulse basis. Current-mode control offers some advantages over voltage mode. Most notably, it adjusts more quickly to input changes, as it doesn't have to wait for the delay in the error amplifier or output filter. However, this isn't very important in designs with constant input voltages, such as distributed power designs with a dc rail available for the core power.

You should also optimize the switching frequency of converters. Switchers always generate some amount of ripple on the output voltage. Even a low ripple can adversely affect system operation. Ripple can be minimized by improving output filtering and increasing the pulse-width modulator's frequency. If a system operates on analog signals within a certain frequency range, try to operate the switching regulator at frequencies outside of this range. In addition, watch the harmonics.

Most integrated switching regulators are driven from either an internal free-running oscillator or fixed to an external clock source. It's best to try to lock the switching frequency to an available clock. If not locked to a stable clock source, the oscillator frequency may vary and change the ripple frequency, which may cause system problems.

When multiple high-power ICs are used in a design, it's often best to provide a separate power converter for each device. This allows you to place the converter next to the device being powered, reducing peak transients and the resulting electromagnetic interference (EMI).

Make sure multiple regulators are synchronized. Asynchronous switchers can cause interference based on the products of the two oscillators. Try to run two switchers on opposite edges of the same clock source. This provides deterministic noise components and minimizes transient amplitudes.

Leave room around each regulator, including the area above it, for airflow. Even a good switching regulator dissipates power. Also, be careful when placing components and traces near switching inductors, because electromagnetic coupling can cause serious problems with local circuitry.

As with all systems that combine high-speed digital and sensitive analog circuitry, it's best to isolate ground and power current paths. Digital switching inherently causes transient currents that return across a ground path. Providing a separate ground path for the digital currents reduces the ground noise (sometimes called bounce) presented to analog circuitry.

Ground circuits can use either single or multiple ground planes. If one ground plane is used, isolate the area connected to the analog circuitry from the area connected to the digital circuits (Fig. 2). Route an analog ground island to connect to all analog connections and place a digital ground plane under the digital circuitry. The analog and digital ground connection should be close to the power source or right at the power connection on the circuit board.

The digital ground plane should be masked from running under or near sensitive analog circuitry. Although the second ground plane adds cost to an assembly, it may provide the noise reduction needed to meet specifications.

In the presence of high-voltage potentials, such as on telephone-line interfaces, the area should be masked off from any low-voltage analog or digital circuitry and from associated ground/power planes. This will help prevent noise from coupling into the system and reduce the chance of high-voltage arcing.

Many high-speed CMOS devices, such as those based on DSP cores, often transition from an intense processing mode that uses lots of power to an idle mode that requires only a small amount of power. These transitions can cause extreme changes in current demands–in the order of 20 A or more per microsecond.

At the same time, silicon process advances have driven the core voltages of high-speed devices to 1.3 V and below. To maintain bias tolerances of 5%, supplies must not fall below 1.235 V. Maintaining this tolerance over extreme current variations isn't easy, and it grows more difficult as process technology continues to advance. Moreover, chip designers are always trying to reduce the average power needed by an IC. Consequently, the dynamic range of power requirements (minimum-to-maximum current) will also typically increase.

Be wary that you don't overestimate your power regulator's ability to accommodate extreme changes in current demands. The current peak itself may be within the capability of your regulator, but the specific regulator design might not be able to react fast enough to load changes. This results in voltage-dropout of the regulator during load changes.

If your power regulator can't react quickly enough to the load changes of the high-speed devices in your system, you will need to use bypass capacitors to help out. Bypass capacitors are storage devices that provide energy locally to a device. They average out the energy supplied by the power regulator, reducing the demands caused by the load. Like small rechargeable batteries that act like integrators, bypass capacitors are always being charged or discharged local to the device being powered.

To minimize impedance, bypass capacitors should be placed as close as possible to the power and ground pins of high-speed devices. This helps prevent potential ground bounce and noise from corrupting input thresholds. Ground bounce is the voltage drop that takes place across a ground connection during high current spikes.

Both large and small capacitors will likely be required. Such a combination of capacitors will deliver the load current in steps as shown in Figure 3. It will also ensure that there's enough decoupling to dampen voltage and current spikes. In very high-load transient situations, where the load step is about 100 A/µs, three or more types of capacitors may be needed to ensure that current is sufficiently supplied before the regulator takes over.

The fastest transients will be supported by high-frequency capacitors, the mid-range transients by low-frequency bulk capacitors, and the rest by the dc-dc regulator. Also, dc-dc converters may require capacitors very close to their outputs, often specified by the manufacturer.

A load-current measurement during worst-case activity is a good way to understand /*what load transients you need to accommodate. The load measurement must be made with an accurate current probe between the device being powered and capacitors on the power bus. To measure all of the current being delivered, tap into the device power connections with a high-gauge wire (Fig. 4). Microprocessor and DSP manufacturers often supply a worst-case software algorithm, which creates a sequence of high- and low-power operations that can be used for a worst-case load-step measurement.

Give careful thought to capacitance values and ESR
A relatively large external capacitance with low equivalent series resistance (ESR) is often necessary to minimize peak deviation during large transients. But because this combination can cause stability problems with the regulator, the low- and high-capacitance values must be carefully selected. Don't forget that a regulator is an amplifier, so it can experience all of the problems associated with amplifiers.

For high-frequency transients, a low-value capacitor on the order of 0.01 to 0.1 µF can effectively do the job. Surface-mount ceramic capacitors provide fairly low ESR and low equivalent series inductance (ESL). Plus, they're size- and cost-effective at these values.

There are general rules for calculating the capacitance and ESR for lower-frequency bypass capacitors. If local low-frequency decoupling is inadequate, there will be voltage drops on the core inputs during transitions from low- to high-current modes. These voltage drops can last many microseconds, depending on how long it takes the regulator to adjust its gain and provide the increased load current.

With a typical high-speed design, load current changes can be 20 A/µs or greater. As an example, if a worst-case load step is between 2 A in idle and 10 A at highest performance, the result is a transient rise time of:

tr = Load step required/current required by process

tr = 8 A/(20 A/µs) = 400 ns

Depending on its loop response and characteristics, a typical dc-dc voltage converter has a 1- to 100-µs response time. Due to this relatively slow response, output-decoupling-capacitor characteristics dominate during the initial voltage deviation in a load step. Based on this, additional bulk capacitance is needed to slow down the transient time seen by the dc-dc regulator, along with high-frequency capacitors to slow down the transient time seen from the bulk capacitors. In general, the ESR of a bulk capacitance should be set so that output voltage ripple and voltage spikes stay within the specification of the device being powered.

To establish a voltage budget, you must understand all contributors to voltage variations, including the set-point tolerance of the regulator, the ripple voltage, and transient noise. For example, if you need to maintain 5% of a 1.8-V core voltage, you may need to maintain a total voltage tolerance + switcher ripple + transient noise budget of ±90 mV. If you can maintain ±60-mV tolerance on the regulator (with ripple), that leaves ±30 mV for transients from load steps. If the maximum load step from the design is 2 A, then:

ESR = dV/dI

ESR = 30 mV/2 A = 15 mΩ

where dV = transient window and dI = maximum load step.

To reduce the ESR of the storage capacitance to this level, you may need to use many capacitors with an ESR of 100 or more milliohms in parallel. This approach may also offer size and placement advantages, especially with surface-mount technology. To verify proper capacitance, you must know the transient response for the regulator being employed. The capacitance needed, assuming ESR is 0 Ω _is:

C = (dI × dt)/V

A regulator that takes 10 µs to settle after a 2-A load transient requires the capacitance to be:

C = (dI × dt)/V = (2 A × 10 µs)/30 mV = 666 µF

In this example, four 180-µF capacitors with an ESR of 60 mΩ or less will do the job. It may be more cost-effective to use many higher-ESR capacitors in parallel than expensive capacitors with the needed low ESR. The tradeoff will be board real estate and part count versus cost.

From these equations, you can take points to get a feel for various ESR and capacitance combinations that will fall within your voltage-noise budget. Keep in mind that this is a fairly conservative analysis. Using a reaction time for power sources assumes that the sources don't compensate for the change in current demand until time (t) has passed, and then it can deliver all of the current required. It's also conservative to assume that the IR drop is the full drop for the entire period in which the capacitor discharges.

If you don't supply sufficient power into a regulator, you can't get it out of the regulator. In some high-load transient designs, the input circuitry could supply more than enough average power into the regulator, yet it may have limited load-transient capability. To provide energy during high-demand situations, you may have to provide a series input coil followed by a low-ESR storage capacitor at the input. The added input coil will supply the additional storage needed to increase the necessary di/dt during these situations.

Though all designers are familiar with Ohm's Law, many take too much for granted when designing power and ground connections for a device. Some designers simply provide large copper traces on power and ground connections to pass the current needed. Copper will pass the current, but with a high-performance device, you must minimize the voltage drop across the power connections.

A 1-oz copper (0.00135 in. thick), .5-in. wide trace has a resistance of about 1 mΩ/inch. A 4-in. run will thus have 4 mΩ of resistance. If 10 A is passed, there will be a 40-mV drop across the board alone.

Also be aware of parasitic series inductance from vias and connectors. Vias on a power plane can result in very high inductive reactance that produces a voltage drop well beyond the limits of any low-voltage process. Try to stay far away from running power connections through vias, even if you provide stitching. Position your regulator close to the device you're powering to reduce board impedance.

All power connections create electromagnetic fields, especially during high transient conditions. For this reason, route high-impedance or sensitive analog traces away from power runs. If a trace needs to pass a power run on another layer, cross it at 90° angles to minimize mutual inductance and reduce coupling.

If you're forced to position the regulator a distance away from the devices being powered and you can't dedicate a power plane (or the board is done and things look bad), try using bus bars to reduce impedances and clean up the power. They can be used for both power and ground connections. Don't forget to study the effects of airflow when using bus bars. If employed properly, they can be used to direct airflow where most needed.

You may also consider running a short sense trace back from the device you're powering. This can help set the proper voltage at the load, though it may result in additional noise issues if the sense line isn't carefully routed and compensated. Keep in mind that the sense line drives an input to the regulator's error amplifier, which controls the overall gain. Long sense traces can cause instabilities, so you need to properly study the regulator's control loop.

Capacitor technology has seen steady improvements over the last few years to help provide lower ESR and larger capacitance in smaller surface-mount packages. Aluminum electrolytics are still the lowest-cost bulk capacitors, but they're physically large and typically exhibit high ESR. Tantalum capacitors have been the workhorse for bulk capacitance, yet they too are large, and their ESRs may be too high for the capacitance needed with high-transient load situations. Some manufacturers are starting to offer new types of electrolytic capacitors with specialty polymers for the cathode material. These components, however, are still quite pricey, have a low ESR, and come in small sizes that reflect the lower voltage ranges of new process technologies.

Noise on a power bus often results in high EMI, which may bring up regulatory issues during system testing. Load transients and ripple voltage across a power bus cause radiation at the frequencies involved and their harmonics. Reducing noise via the methods discussed may significantly reduce system EMI.

Too often, intermittent system problems relate back to power problems that could have been rectified during the beginning stages in a design cycle. A solid study of the power planes early in the debug stage might uncover fixable specification violations, thereby eliminating potential residual problems before they surface. Take the following worst-case measurements.

When measuring noise on a power bus, understand what you see. Large amounts of energy radiate from power buses, so a less-than-ideal probe without proper ground connections can cause improper measurements. Use one or two high-frequency probes with a small ground stub, as shown in Figure 5. A ground wire of as short as two inches will result in bad measurements.

The oscilloscope must clearly display and trigger up to the noise frequency to which your circuit might react. At minimum, use a 200-MHz oscilloscope and probe. For best results, use one probe for the power connection and another for the ground connection. Then set the scope to a math function that adds the two inputs, with one probe set to invert. This differential method reduces the risk of ground currents that may occur when using a single probe. When making differential measurements, it's often best if no ground wires are used on the probes.

Trigger the oscilloscope properly using normal mode, with the threshold adjusted for extreme peaks. Make two measurements, one with the scope triggering on the positive edge for the positive peak voltage measurement, and the other with the scope set for negative slope trigger for the negative peak measurement. The difference between the two numbers is the peak-to-peak noise voltage. Measure the frequency of the noise by simply inverting the periodic time of the specific noise being viewed.

To measure high-frequency transients, set the scope for a faster sweep. Look at components above a few megahertz and use the technique described previously to measure the peak-to-peak voltage and frequency. If you see more than one noise component, pay attention to the one with the highest amplitude. In some cases, noise components may be at frequencies higher than the device can respond to, and thus not cause problems. To view noise components in the kilohertz range, set the scope to a low sweep frequency. Low-frequency noise often results from system operation, possibly a function of a processor executing high-performance subroutines along with low-power idle modes. Changing the software operation of the devices being powered can help identify the noise source and potentially lower peak current.

Use a spectrum analyzer to quickly identify noise components that may cause problems. It will also help identify the noise source. The ripple voltage created by a switcher may be riding on another lower-frequency component, and will almost always have higher-frequency noise on it created by high-speed digital processing.

Taking the time to properly observe the power supplied to high-speed devices is worth the effort. Some bench time early in the prototype debug stage can save a lot of debug time later on.

Very often I see system power problems surface as unrelated system anomalies. Power problems can be quickly resolved or avoided altogether by investing sufficient time in your power design from the earliest stages.

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