Electronic Design

Digital Power Architecture Arrives

Processor performance is increasingly limited by its transient power demands, which also impact the cost of the power solution. Power-supply noise is proportional to the maximum current rate of change, di/dt. With each new processor generation, di increases and dt decreases, causing a dramatic increase in supply noise.

As a result, processor voltage regulation requirements are tougher to meet. New power approaches with im-proved regulation accuracy, higher efficiency, and faster transient response are needed. Also, shrinking OEM design cycles require power solutions that are easier and faster to design.

To meet these requirements, designers are working on several new power architectures. One new approach is gigahertz transient regulation and digital multiphase control—together known as the digital power architecture.

Processor power-supply transient noise (droop/overshoot) can be segmented into three specific time domains. The third-droop and overshoot events, which measure greater than 1 µs, occur at the node between the VRM and the motherboard and at the node between the motherboard and the microprocessor socket. The third droop is controlled by the voltage regulator's filter capacitors and its control loop. The second droop and overshoot, ranging from 10 to 100 ns, take place at the node between the microprocessor's socket and the microprocessor's package. The second droop is controlled by package capacitors. And the first droop and overshoot, which are less than 10 ns, occur at the node between the microprocessor's package and the chip itself. The first droop is controlled by on-chip capacitance and transient regulation.

Gigahertz transient regulation is located very near the processor to minimize the amount of parasitic inductance between the regulator and the microprocessor. The transient regulator reduces the amplitude of high-frequency (first and second droop/overshoot) transient events. A digital multiphase regulator with a programmable digital control loop provides the core voltage regulation and third droop/overshoot transient control. By digitally controlling the core-voltage regulation, complex-operating modes are implemented to optimize performance.

For example, current measurement errors in traditional analog solutions can be calibrated to optimize dc regulation accuracy. The digital controller can sense and react to a transient event and change to wider bandwidth control modes for improved transient response. This active transient management increases loop bandwidth "on demand," allowing less output capacitance, a smaller footprint, higher efficiency, and lower cost. A user-configurable digital control loop enables faster design, since loop compensation can be optimized in real time without changing components. This minimizes board spins and lab time.

Digital multiphase regulators can be used with or without gigahertz transient regulation and deliver the benefits of precise dc accuracy, improved third-droop transient performance, and ease of design. Yet when the complete digital power architecture is implemented, the core voltage noise is reduced significantly across a wide bandwidth. This ultimately boosts processor clock speed and system performance. As processors continue to march to 10 GHz and processor operating voltage shrinks, new power-system architectures like the digital power architecture will become a requirement.

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