Electronic Design

Dynamic Performance Is The Mantra For Analog And Mixed-Signal ICs

Third-generation communications applications are calling for improved dynamic range over a much wider bandwidth.

All anyone seems to be talking about lately is dynamic performance, dynamic performance, and... dynamic performance. It doesn't matter if it's a broadband amplifier or a high-performance, high-resolution data converter. Either way, every analog and mixed-signal data-converter designer is reciting dynamic range at higher frequencies and wider bandwidth. This specification takes on even more meaning as we migrate to 3G cellular and wireless applications, where data rates and functionalities are greater. Suppliers are determined to obtain it in miniature packages at lower voltages and prices.

Analog and data-converter vendors have been efficiently catering to the ongoing needs of the 2G cellular and wireless communications systems around the world. As OEMs cranked out compact handsets featuring more bells and whistles, base-station makers concentrated on wider bandwidth, additional channels, and higher output power. Suppliers of analog and mixed-signal ICs responded by promptly answering the call for adequate dynamic performance at the desired frequencies and bandwidth. They also put the right amount of features on board.

Now, the move toward next-generation communications standards has redoubled the pressure on suppliers of amplifiers and data-converter ICs. As we enter the next millennium, 3G communications specifications are being tweaked and finalized as standards are being put into effect. Makers of 3G cellular phones; broadband software radios; and multimode, multicarrier base-station transmitters are seeking much higher levels of performance. They want it in a minute footprint, without sacrificing power and cost. So newer products will be slimmer, as well as more elegant and powerful. They'll handle voice and data concurrently. Plus, these systems will cost less and work longer using the same battery source.

Meanwhile, direct-conversion, or no-IF, transceiver designs are winning popularity in radio receivers. Suppliers of analog and data-converter ICs are feeling pressure to significantly increase on-board features, slash the external component count, and consume a fraction of the power of previous-generation devices.

Aside from that, they must possess the processing ability to deal with IF signals closer to the antenna. Designers are exploiting state-of-the-art deep-submicron CMOS processes to meet the conflicting requirements of speed, resolution, higher on-chip density, and lower system cost. In designs where CMOS is inadequate, especially at low voltages, they're exploiting biCMOS. And when CMOS and pure silicon-based biCMOS run out of gas, some developers are going after SiGe heterojunction-bipolar-transistors (HBTs), or simply bipolars, to meet performance goals.

Advances Propel Software Radios
Concurrently, advances in digital signal processing (DSPs) and high-speed analog-to-digital and digital-to-analog converters (ADCs and DACs) are pushing designers toward wideband digital receivers or universal software radios. Faster, high-resolution data converters with good linearity and wider dynamic range at higher frequencies also are emerging. When coupled with the quantum leaps in DSP technology, those converters are making wideband software radios feasible for many of the commercial, wireless-communications applications now coming out. Soon, developers will be able to deliver a single analog front end with sufficient horsepower to handle all of the channels over a wide bandwidth and pick out the right signal from the incoming frequencies (Fig. 1).

By replacing the traditional superheterodyne transceiver, universal software radios usher in an era of programmable transceivers. Multiple analog and digital cellular standards can be supported through reprogrammability. That aspect will allow users to quickly adapt their radios to upcoming standards via easy software upgrades.

As the makers of wireless handsets and infrastructure equipment prepare their transition to 3G specifications, they've turned their backs just long enough to let an interim architecture gain popularity. Enhanced data rates for GSM (EDGE), with 384-kbit/s data transport capability, are being put in place to deliver wider bandwidth and increased capacity. Labeled as a 2.5G standard, EDGE is a cooperative effort between proponents of GSM and IS-136. Its goal is to establish a common, high-speed standard that capitalizes on the established 2G infrastructure.

As National Semiconductor's John Steininger puts it, EDGE is the harbinger of how 3G applications will look. He adds that as these emerging standards employ newer modulation and demodulation schemes for faster data rates, the transmitters and receivers must be accordingly redesigned. Newer amplifiers and data converters must comply with these requirements.

For instance, EDGE implements an 8PSK modulation scheme to achieve a higher data rate of 384 kbits/s. This requires that the receivers and transmitters in the base stations be modified, as well as the transceivers in the handsets. There's a tremendous push in the analog and mixed-signal design world to achieve greater dynamic range over a substantially wider bandwidth. Designers are even talking about attaining 100-dB spurious-free dynamic range (SFDR) at a 200-MHz signal frequency with a bandwidth of 30 to 35 MHz.

This level of dynamic performance cannot be achieved without lowering the noise floor and improving the integral-linearity (INL) error. Pressure is mounting to significantly slash the noise generated by the amplifiers and the data converters employed in the new designs. Then, the signal-to-noise ratio (SNR) of the receivers and transceivers could be high enough (greater than 75 dB) to decode even a weaker signal. They would thereby be able to extract and process both strong and weak signals with the same level of integrity.

In a similar vein, designers are working to drive 14-bit transmit DACs to a 100-dB SFDR and a greater than 85-dB SNR over the full cellular bandwidth. At the same time, the operating frequency for these parts is being increased. Recent 14-bit DACs have demonstrated a 75-dB SFDR at 26 MHz and a 74-dB adjacent-channel power ratio (ACPR) sampling at 65 Msamples/s. The thrust is to propel that performance further, reaching greater than 85-dB SFDR and about 75-dB SNR over the 35-MHz bandwidth within a year. Designers also are striving to obtain 16-bit resolution for such parts. Of course, the major competitors have targeted 100-dB SFDR over the entire cellular bandwidth for 16-bit DACs within the next two years.

Others have in mind the creation of a perfect 14-bit solution by the end of this year. Analog Devices, for instance, plans to refurbish its 14-bit transmit DAC, says Stephen Lajeunesse, project marketing manager. To ADI, "perfect solution" means attaining theoretical SNR and SFDR specifications for the 14-bit transmit DACs. The manufacturer is refining its existing architecture by tweaking the current switches and sources for better linearity. It's also reducing the noise floor by cleaning up noise sources like substrate, clock jitter, thermal mismatch, and other such functions.

Climbing that same ladder are the intermediate frequencies generated. They're putting stress on the sampling and update rates of future 14-bit DACs. To simplify upconversion using a mixer or analog multiplier, higher-resolution transmit DACs will have to reconstruct output waveforms at frequencies beyond 400 MHz. The path will then be clear for the development of broadband multimode, multicarrier transmission in the next-generation cellular base stations.

Initially, the plan will be to generate an IF around 200 MHz, and then slowly extend that capability to 400 MHz within the next couple of years. Such progression will simplify the upconversion to the desired carrier frequency for transmission. Traditionally, the DACs have generated single-carrier TDMA signals at much lower frequencies, which require complex mixers and local oscillators or analog multipliers for upconversion.

Note the widening channel spacing in the newer standards. As it stretches, ACPR performance gets more attention to ensure minimal unwanted distortion in the adjacent channel bands. To remove the undesired signals from those bands, designers are incorporating on-chip digital-interpolation filters. Migration to 0.35-µm CMOS processes has made this integration feasible. In fact, Analog Devices demonstrates it in its latest 150-Msample/s, oversampling 14-bit transmit DAC (see "Wideband DAC Fosters Multicarrier, Multimode Transmission," Electronic Design, June 14, 1999, p. 37).

A Boost To In-Band Performance
By suppressing the first set of images, the on-chip digital filter enhances the in-band performance of the multimode, multicarrier design. It also simplifies the use of the analog reconstruction filter that follows the digital-to-analog converter output. The challenge is to improve this on-board digital-interpolation filter to afford greater flexibility and higher output frequencies, while providing an ACPR of over 65 dB at IFs of 70 or 140 MHz. Consequently, data-converter designers are exploring higher levels of interpolation filters, going from current 2X to 4X interpolation. Integrated, higher-order filters must start appearing sometime before year's end.

Aside from dynamic performance, the new standards are demanding greater linearity over wideband operation. The architecture must be refined to achieve better ac performance at high sampling rates and wider cellular bandwidths. Developments indicate that the INL error is being cut to below 2 LSB, with efforts to achieve 1 LSB in the near future. But many designers feel that reaching 1-LSB INL in 14-bit or higher-resolution DACs is a bit of a stretch. A more reasonable specification is 2 LSB, which is possible with clever designs.

On the ADC front, suppliers are concentrating on raising the dynamic performance bar at higher and higher input frequencies and bandwidth. A 14-bit, 65-Msample/s ADC with an SFDR of 100 dB and an SNR of 75 dB has been introduced. Now, designers are contemplating pushing the sampling rate to over 300 Msamples/s, while trying to hit an input bandwidth above 1 GHz.

That's several times better than the input bandwidth of current ADCs. To realize that kind of bandwidth, designers are planning to incorporate broadband sample-and-hold circuits and amplifiers at the ADCs' input end. Meanwhile, at the digital end, they're exploring ways to combine such high-performance ADCs with digital downconverters in order to directly link them with follow-on baseband DSP processors.

To support faster outputs, these devices will opt for low-voltage differential signaling. As the converters begin exploiting the benefits of deep-submicron CMOS processes and operate at voltages below 2 V, insufficient signal headroom will be a major challenge. Differential input and output techniques will come to the rescue of these low-voltage, high-performance ADCs.

The wideband amplifiers that drive these speedier ADCs must move forward at the same pace. Thanks to advances in CMOS and biCMOS, the horizon holds the required faster slew rate, higher output drive, and rapid settling times with single-supply operation and extremely low quiescent current. From today's 14-bit accuracy, suppliers are readying 16-bit versions with the same bandwidth at 3-V operation. And full-power bandwidth is being driven to 350 MHz at 5 V and below.

As data-converter designers begin to tap 0.25-µm and finer CMOS geometries, suppliers will be motivated to bring RF functions, such as mixers, local oscillators, and amplifiers, on board. Some visionaries even foresee the integration of RF with ADC, DAC, DDC, and DSP on the same monolithic chip (Fig. 2). In short, the integrated ADC front end will evolve into a full-fledged radio transceiver, including an on-chip low-noise amplifier (LNA) and power amplifier. It will facilitate the concept of a direct-conversion receiver.

In handsets, where the output power needed is below 1 W, integrating the power amplifier on board is commercially feasible. Designs and fabrication processes are rapidly advancing to deliver a phone-on-a-chip in the next few years. But implementing it in the base-station transceiver, where over 100 W of power is delivered from the power amplifier, brings up another question altogether.

To realize this degree of integration, manufacturers will tap a biCMOS process with SiGe bipolar transistors for RF implementation. Needless to say, conventional biCMOS will eventually progress to deliver ultra-fast bipolar transistors that can match the speeds of SiGe bipolars at a lower cost. Until the analog CMOS migrates to 0.25-µm design rules, however, putting all of the RF, analog, data-converter, and DSP functions on one chip is an arduous task. Presently, the CMOS process exploited by analog and data-converter designers is the 0.35-µm geometry. The transition to 0.25 µm is projected to begin around the end of this year.

New standards like EDGE and 3G seek power amplifiers with better output linearity and efficiency. Sure, gallium-arsenide-based MESFETs and HBTs continue their stranglehold on the power arena. This is especially true in the handset applications, where higher output power at low voltages is the name of the game. But the scenario in base-station applications is rapidly changing. The silicon-derived, lateral-diffused MOS (LDMOS) transistor has recently advanced in linearity, efficiency, peak power capability, input/output impedance, and cost/watt features. These features improve its position in the 2-GHz arena.

Key proponents have addressed the bias-current drift problem that's plagued this structure at peak power levels of 100 W and above. Actually, the above improvements have further enhanced the long-term reliability and ruggedness of the silicon-based power transistor.

LDMOS Sets Sights On Wireless
Life for LDMOS devices also has become easier with the availability of 28-V power supplies. LDMOS is poised to make inroads into the power sector of the upcoming wireless-infrastructure systems. Major developers tout their transistors as viable solutions for linear power amplification in wideband-CDMA (W-CDMA) and IMT-2000 standards-based wireless base stations, which operate at frequencies up to 2.4 GHz. Several are even prepping power modules that include the improved LDMOS power transistors, starting at 50 W and going up to 120-W peak output power.

Some of these modules will enter production in the first half of the year, nurturing efforts to get even higher output power and better power-added efficiency (PAE). At RF frequencies, LDMOS-derived power amplifiers still trail behind their GaAs counterparts in power efficiency. Narrowing this gap is the central focus for supporters of this technology. Providers expect to accomplish that task within a year or two, while squeezing more juice out of the power amplifier. Ongoing research activity suggests that the makers of LDMOS power transistors intend to achieve a 30% to 35% improvement in the output power within a year's time frame.

Meanwhile, work is in progress to scale these devices to lower voltages, suiting them for new-generation cellular phones. In this case, 1- to 2-W output power at 2-GHz operation suffices. By refining parasitics and feedback capacitance, suppliers hope to achieve nearly 60% PAE at greater than 1-W output. LDMOS would then stand as an attractive alternative for new-generation handsets, which GaAs solutions dominate today.

The SiGe HBT also is in this power race, eyeing the design slots in emerging cellular phones. Some key vendors have released 3-V, SiGe HBT-based power amplifiers capable of providing 35-dBm output power with 50% PAE. They've been crafted for use in 900-MHz GSM systems, but improvements are in the works to raise the frequency spectrum to the 1.8- to 2.0-GHz range. Developers want to make such units suitable for a line of GSM products using 1800- and 1900-MHz carrier signals.

Proponents of GaAs aren't going to sit by idly, however. They're watching these developments and aggressively addressing the cost issues. Cost has been a major hurdle for these parts. To maintain the dominant position of GaAs, suppliers are migrating to larger wafers. This move should cut costs while providing the same benefits of performance and high efficiency.

In the handset arena especially, the trend is to convert dual-supply designs to single-supply operation. Designers are seeking alternatives to the GaAs metal-semiconductor FETs (MESFETs) and pseudomorphic high-electron-mobility transistors (pHEMTs) that use negative and positive supplies for amplification. So it's not surprising to see gallium-arsenide bipolars flexing their muscles on this plane.

Meanwhile, silicon-carbide-based MESFETs are slowly but steadily inching forward to steal the spotlight in future infrastructure equipment. With the recent demonstration of 2-GHz SiC MESFETs operating from one 48-V supply, their prospects for serving the power requirements of next-generation base stations look bright. Although the power density offered by these MESFETs is high (4 W/mm at 1.8 GHz), the output power is limited to 10 W continuous. They're likely candidates for the driver section in the near future. As power capability improves in a year or two, they also should be ready to deal with the main power amplifier.

With so many technologies available for power amplification in next-generation systems, the competition is bound to heat up. Unlike previous years, there won't be one dominant technology. Selecting the right solution will depend on the designers' understanding of all competing technologies.

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