The combination of reprogrammability and quick turnaround offered by FPGAs makes them an appealing option for prototypes. These features are also attractive to educational establishments because because students can quickly develop basic system elements and explore a range of options at low cost.
However, by focusing on FPGAs in the academic environment, students will enter the world of employment with a rather limited view. Many young engineers may wind up with only a cursory knowledge of other available technologies.
An example can be seen with in-line data buffering. For a number of years, FIFOs and multiport memories have been the designer’s first choice for data buffering. However, the steady growth in FPGA memory density has many designers now opting for on-chip memory.
This change offers advantages. First and foremost, collapsing multiple data buffers and data-control functions into a single IC will create a more “elegant” solution, reducing component count and board space requirements.
However, there is a cost. As data buses move to rates above 100MHz, they require higherdensity buffers and, therefore, more-expensive FPGAs. Also, a number of performance limitations appear when engineers integrate FIFO or mult-port memory functions into programmable logic. In many cases, discrete components or a combination of a smaller FPGA with discrete devices can create a better solution.
Many engineers graduating today aren’t aware of recent developments in discrete specialised memories, such as FIFOs and multiports. Today, FIFOs are available in a range of densities up to 18Mbits. Read and write ports can be operated independently from each other at speeds up to 250MHz, and DDR options can boost performance up to 20Gbits/s/port. Port-selectable features allow the user to select bus width, I/O voltage, data rate, and synchronous or asynchronous operation. Integrated flag operations increase device functionality. Most importantly, pin-compatibility across product lines allows designers to upgrade easily.
Multiport memories have progressed similarly, now offering widths ranging from eight to 72bits. They also can support different bus widths on each port. Speed ranges up to 200MHz in synchronous mode or 10ns in asynchronous mode, and densities run up to 36Mbits. The range of currently available devices supports core voltages of 5, 3.3, 2.5, or 1.8V, and I/O voltages of 5, 3.3, 2.5, selectable 3.3/2.5, or 1.8V. There are also specialised functions such as full-boundary counters, independent byte enables, collision detection, interrupts, semaphores, and busy arbitration. As with FIFOs, multiports are available in a wide variety of density options in the same package.
FPGA-based data buffers face performance limitations as more FIFOs enter the design. Typically, designers use tools to map multiple FIFOs automatically into a single physical memory block and generate the logic necessary to time-domain multiplex between multiple user-specified FIFOs. However, since each independent FIFO port must be multiplexed together, the maximum operating frequency of each FIFO port is inversely proportional to the number of FIFOs mapped into a design.
While each FIFO operates independently with its own clock, data, control input, and status flags, total memory bandwidth between them is shared. When a FIFO read or write operation is initiated, sequencer circuitry accesses the physical memory in the fast time-divisionmultiplexing clock domain. The sequencer then transfers information back to the clock domain of the FIFO port to complete the memory access.
Due to the clock-domain transfers, FIFO performance is inherently limited by the sequencer’s speed and the number of FIFOs. Some FPGA vendors recommend against partitioning their devices into more than 10 FIFOs in high-performance designs.
Configuring an FPGA to provide dual-port capability can also cause problems. In many of these applications, the FPGA is connected to an ASIC.
Because the ASIC can’t function until its input data is stable, setup time affects maximum speed. Using larger aggregations of memory in FPGAs will push some of the memory further away from I/O and logic gates. As a result, internal write pulses can vary in length and contribute to longer setup time.
An FPGA with an internal speed of over 200MHz can exhibit a maximum speed of 120MHz or less. In contrast, setup time and, therefore, maximum speed for a 200MHz dual-port memory remain constant and significantly faster than an FPGA implementation across the entire memory density range. If the designer implements the design with a smaller FPGA and external multiports, performance will only be limited by the FPGA’s I/O (Fig. 1).
Integrating a data-buffer design into an FPGA often offers significantly reduced footprint, particularly at low densities. This may not be the case at higher densities, though.
For example, moving from a small 40kgate FPGA to a large 8Mgate device will increase package size from a 256-pin ball grid array (BGA) to an 1152-pin BGA. In contrast, FIFOs and multiports are available in the same 256-pin BGA package, regardless of density. At high densities, designers can often achieve greater efficiency by combining a smaller FPGA with an external FIFO or multiport memory.
A memory cost-per-bit comparison between FPGAs and FIFOs illustrates a key difference between discrete memory devices and FPGAs. As with any discrete memory device, cost-per-bit for FIFOs and multiports decreases at a fairly constant rate as densities rise. While memory embedded in an FPGA comes at a higher price than discrete devices, it tracks down at a rate similar to FIFOs and multiports up to approximately 256K. Above that, however, the cost-per-bit of FPGA memory starts to increase rapidly.
If an FPGA’s memory capacity is exceeded, the designer must move to a larger device. This leads to unnecessary additional logic, which drives up cost, and use of more board space. Designs that employ FIFOs or multiports can be expanded by adding another memory IC, or by replacing the existing memory with a higherdensity device in a pin-compatible package (Fig. 2).
Altering a design using pincompatible discrete FIFOs and multiport memories is fairly straightforward. In contrast, an FPGA-based design will typically require recompilation, timing changes, and several other adjustments.
Reliability should also be considered. Shrinking process geometries and lower operating voltages have helped to increase memory density. However, the combination of reduced capacitance and reduced voltages also increases soft-error rates in SRAM cells. FPGAs tend to use smaller, lower-voltage geometries than FIFOs and multi-ports, thus they often have higher softerror rates.
For data-buffer applications that require memory densities under 512K and clock rates under 100MHz, integrating the design into a single FPGA often provides the best solution. However, as memory requirements increase and clock rates rise, designers will find that the high-performance and low-cost characteristics of discrete FIFOs and multiport memories deliver distinct advantages.