Anyone who has seen the transformation of the electronics design market from fixed-chip development to programmable devices can attest to the dramatic impact that FPGAs have made on both electronic product development and the miniaturization of electronics. As these devices get larger and more capable, an increasing number of designers are marching toward FPGAs each and every day. According to research firm Gartner/Dataquest, this year will see nearly 89,000 FPGA design starts, and will swell to 112,000 in 2010—some 25 times that of ASICs.
In regards to targeting ASICs vs. FPGAs, the question these days is not "can I put my design into an FPGA?" More often, the question is, "Why shouldn’t I put my design into an FPGA?"
The dramatic differences in time-to-market and NRE cost have shifted the choice to FPGAs for all but extreme (speed, size, power) applications. This is where Moore’s law meets Einstein! The last time I checked, the speed of light had not changed. FPGA vendors have harnessed the benefit of die shrinkage to increase the speed of their silicon while reducing the power consumption with each and every technology node. These improvements have expanded the opportunity for these devices into more market segments.
It’s not easy to design an FPGA nowadays. Designs are getting larger, according to a survey conducted by EE Times. And though FPGA design complexity has escalated, the tools that this class of design engineers has at their disposal are insufficient. I guess you could say that these are hard times for FPGA designers. Many design teams are applying the same tools and methodologies that they previously used for ASIC design into their new FPGA creations. This trend is growing as designers march toward FPGAs. In the United States, the average gate count for an FPGA design is 2.4 million gates, increasing to more than 4 million gates by 2008.
Even with sophisticated tools, FPGA designers suffer from the same long verification cycles as their ASIC brethren. The EE Times survey reveals that the top three problems are functional verification, getting the design to work on the printed-circuit board, and timing closure.
Using a rigorous verification methodology is not enough. Traditional simulation tools help shake out the intent of the design, but they can’t anticipate the unintended effects of placing that design onto the FPGA device. This is especially true where third-party IP is used. Indeed, with 2+ million-gate designs, more than one-third of each design is composed of reusable IP. We see this with every customer, and I can’t recall when a design did not use FPGA-vendor IP and third-party IP.
FPGA complexity and speed increase with every passing day. With the right tools, the FPGA designer can apply their art to creating great products and break the cycle of hard times. GateRocket, for instance, recently released a new class of FPGA verification technology in a practical, affordable package that combines both software and hardware to attack the problem.
EDA people are always looking for ways to grow their market share. Given the explosion in FPGA starts, maybe it’s time to apply some of their R&D resources in an area where opportunity seems boundless.