Electronic Design

Future-Proof Low-Profile 1U And 2U Systems With High-Speed Connectors

Choosing connectors that meet increased speed and density requirements for low-profile 1U and 2U rack-mountable systems is a complex task. Increases in signal-pin counts and power consumption have turned system packaging design for optimal airflow into an increasingly difficult challenge.

Common to network interfaces, storage, and telecom equipment, these lowprofile systems require long-lasting connector configurations that can survive next-gen upgrades.

Several connector configurations are available to meet requirements for 1U and 2U systems. Mezzanine and coplanar board-to- board configurations increase overall system performance and flexibility, especially in compact designs with a defined envelope and sparse board real estate.

Due to the complexities involved, it is important for engineers to include connector and contract manufacturers as well as silicon vendors and printed-circuit board (PCB) fabricators early in the design process. Most manufacturers will walk through the part selection process with the engineer to help determine which interconnect solution meets the necessary speed, density, cost, quality, and long-term reliability requirements. This will ensure the engineer chooses the optimum configuration.

Actually, some connector manufacturers will create models that show users how high-speed channels will perform in their specific design. Also, they can create an electrical model for full channel analysis, which the customer can use to predict the electrical performance of a system before tooling it.

To uphold a system’s longevity, engineers must account for next-generation advances in their current designs. This is a tricky task because racks used in expensive 1U/2U systems must last through two or more generational upgrades.

For example, a 20-circuit connector today may need to support higher data rates for Gen 2 or Gen 3 protocols in the future, which typically increases the pin count. As a result, many engineers are designing their systems with headroom for increasing speed capabilities. This helps ensure a product can incorporate new technologies. It also ultimately reduces the cost of system upgrades.

Operability issues, such as airflow and board density, go hand in hand in the design of small-envelope systems. Dense boards generate a significant amount of heat and require more airflow. Early in the design process, it is important to consider adequate cooling for both current and future needs. Cooling utilities, i.e., heat sinks and fans, improve thermal management by spreading heat and blowing air through the box.

However, if hot air simply recirculates through the system, the equipment may still overheat. Open space in a design helps introduce fresh air, minimizing the amount of hot air present. Ultimately, the necessary amount of airflow determines the stack height between boards, so all components must be strategically spaced within the overall system.

Compact high-speed configurations can lead to compromised signal integrity, so designers must find a balance between optimum transmission speeds and envelope size. It is also critical to create a system satisfying both bandwidth and space requirements.

As data speeds increase, more connector shielding is required to protect against crosstalk during data transmission. Grounding connector pins helps facilitate the shielding process, but it can increase the connector size. Plus, taller stack heights increase signal path distance and may impair signal integrity.

PCB adhesion is another consideration since components are typically surfacemount (SMT) or through-hole. SMT devices may have J-lead tails, ball-grid array (BGA), or solder-charge technology and sit on the top of one side of a board. SMT adhesion provides benefits in its ability to place components on both sides of the PCB and is typically preferred from a signal-integrity standpoint.

One drawback of SMT is the lower adhesion force to the board and longer exposure to higher oven temperatures than through-hole, wave-solder, and press-fitcompliant components require. Fortunately, there are interconnect configurations that address these low-profile 1U/2U design challenges.

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Available in a variety of pin counts and stack heights, mezzanine connectors enable a flexible board-stacking approach, permitting designers to take critical system functionality off the motherboard without sacrificing performance (Fig. 1).

Mezzanine cards provide practical benefits such as doubling PCB real estate. Applicable to both sides of motherboards or used for multiple boards in a stack, SMT configurations can be especially helpful.

Key chips or controllers, processors, or FPGAs are deployable on mezzanine cards. This reduces the layer count and cost of the main board. It also allows for future system upgrades by making it easy to plug in the latest microprocessor when it becomes available.

Engineers often employ mezzanine cards for I/O options after building the box. Since mezzanine boards tend to be small, they can also be cost-effective for very fine pitch packages like FPGAs (Fig. 2). If a component has a yield or reliability problem, mezzanine cards can make them easy to replace in production or even in the field. Mezzanine card assemblies can be easily outsourced, leveraging outside technical resources for design support and competitive cost. Additionally, they can ensure product longevity (Fig. 3).

Signal clarity As system speeds increase, designers must be mindful of signal clarity and any degradation of multi-gigabit signals routing throughout the system. Faster speeds equate to higher noise sensitivity. Before choosing an interconnect, designers need to ensure that any channel they design operates within the bandwidth of the selected serializer/deserializer (SERDES) or ASIC.

As a result, designers often ask connector manufacturers to help verify a system’s signal integrity by creating electricalchannel models for predicting end-to-end signal performance. This involves a signalintegrity engineer working with the customer to create analytical channel models to monitor transmission-line and noise performance.

Software packages like Ansoft HFSS or CST Microwave create virtual channel models by simulating the major elements of the high-speed signal path. Designers can import these channels into their circuit simulation tools to predict the overall system performance at varying data rates. These models provide design verification earlier than prototype testing and before a significant capital investment.

For years, numerous committees have been standardizing certain protocol signal callouts to make it easier for design engineers to configure their system. For example, a committee may standardize the number of circuits for an industry protocol and list the preferable interconnect for the application. In doing so, the committee saves time for designers as application designs become standard, depending on the protocol required.

In 1995, the IEEE standardized the PCI Mezzanine Card, specifying the card size, front-panel opening, connector, and interface protocol. This allowed many suppliers to offer a variety of I/O and special function boards.

In 2006, PICMG created a standard for the Advanced Mezzanine Card (AMC). Without removing the host card, end users could add a hot-pluggable card specifying a standard size, connector, and protocol. This connector provided state-of-the-art, 10-Gbit/s speeds that anticipated present and future needs. Again, a large community of suppliers created mezzanine cards, not only for I/O interfaces, but also for DSP modules, processor cards, and disk drives.

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Similar to mezzanine configurations in the diversity they provide engineers for low-profile design, coplanar boards offer system flexibility for next-generation asymmetrical designs and upgrades. Coplanar board-to-board devices, or peripheral interface cards, enable engineers to design systems with various levels of functionality by offering different boards that plug into the same base card or motherboard.

For ultimate flexibility in providing airflow and density in asymmetrical configurations, coplanar boards offer different offset heights. Thus, the 1U or 2U box can adjust the height of the daughtercard to accommodate I/O interfaces or compensate for component heights in spaceconstrained environments.

With coplanar configurations, users can easily replace boards with upgraded versions to encourage higher performance along with technology advances. Targeted board replacement helps cut long-term costs for those planning to use their system through multiple generation upgrades. Connected end-to-end on the same plane, coplanar configurations offer multiple benefits for storage server, networking, and industrial systems, especially in smallenvelope designs.

Pairing mezzanine boards and coplanar cards provides the ability to customize, upgrade, and effectively reduce the cost of 1U/2U boxes. As with most board-toboard designs, there are tradeoffs to consider when deciding between system size and channel performance. Many tools are available to ease the task of choosing the optimal interconnects.

Knowledge of product enhancements and design tools can save time and ensure proper system capabilities. Making such considerations early in the design process ensures the box will be cost effective and well matched to customer needs, both now and in the future.

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