Demands unleashed by high-speed multigigabit-per-second serial buses continually push the test-and-measurement (T&M) equipment envelope. Some of the latest equipment to enter the fray are real-time oscilloscopes, sampling oscilloscopes, digital communications analyzers (DCAs), time-interval analyzers (TIAs), protocol analyzers, and bit-error-rate testers (BERTs). They all aim to ascertain the integrity of signals working at gigabit-per-second rates. These rates are overtaking the available bandwidth of modern measurement tools.
Serial buses like HyperTransport, RapidIO, PCI Express, and the USB employ packet-oriented communications. In these cases, the addressing information is packaged with the data and sent either over a single path from point A to point B (bit serial) or over multiple paths (parallel). This is a significant departure from the parallel bus architectures of yesteryear, which had address and data buses, or they multiplexed the information over one bus. As a result, T&M designers now face huge challenges in verifying signal integrity.
In particular, accelerating digital data rates make the issue of analog signal integrity more critical than ever before. With ever faster rise times of signal transitions, the analog effects of interconnects begin to dominate system performance. They're no longer restricted to just the transmission medium. Connectors, sockets, pc boards, and other hardware associated with a transmission system are affected as well. Data rates of 10 Gbits/s have become commonplace, and 40-Gbit/s data rates loom on the horizon.
In general, testing at high data rates is more difficult than testing at lower data rates. In addition, detecting irregularities in high-data-rate systems becomes more important because the higher data rates tend to enhance and accentuate irregularities in the signal stream. Here, jitter testing becomes a key measurement parameter.
The ultimate performance metric for high-speed serial links is the faithful measurement of bit-error rate (BER), which is influenced by the amount of jitter in a system (see "Eye Diagrams, Bathtub Curves, And Bit-Error Rates," p. 58). Thus, it's no surprise to see T&M equipment manufacturers huddle more closely with chip manufacturers preparing next-generation high-speed silicon devices for gigabit-per-second serial networks (e.g., Intel, IBM), as well as with connector, socket, package, and pc-board manufacturers.
One major difference between serial buses like PCI Express and parallel buses is the measurement of a bit's logic-level changes. Unlike parallel buses that have two distinct logic amplitudes of 1 and 0, PCI Express uses preemphasis methods in which a signal has two possible amplitudes at each of the two logic levels. At each level, a difference of 3 to 4 dB can exist at the two 0 levels and at the two 1 levels (Fig. 1).
This is one reason why a PCI Express eye diagram measurement must be made as close to the bus' transmitter and receiver as possible, which leads to specialized probe tools. A PCI Express lane can tolerate no more than a few picofarads of capacitance. Otherwise, impedance discontinuities may occur.
Even the most modern high-speed sampling oscilloscopes, which traditionally analyze data transmissions over copper and optical lines, typically possess bandwidths of a few gigahertz and sampling rates of about 5 Gbits/s at most. Analyzing signal integrity at today's high data rates with these scopes is usually done by averaging the data over a long period of time using multiple acquisitions at a lower sampling rate. However, with the constraints imposed by today's shorter design cycles, time is a precious commodity. In addition, many of these instruments can only locate a signal problem, but not its cause. Designers, then, often must make educated guesses for probable causes. So it's becoming clear that even the fastest sampling oscilloscopes need the help of other advanced instruments to obtain accurate analysis of signal integrity.
A MATTER OF PROBING
When verifying signal integrity at gigabit-per-second data rates, the instrument's probe becomes a crucial part of the measurement system. Increasingly, T&M equipment manufacturers are offering specialized probes and probe hardware for more accurate high-speed signal-integrity measurements. As rise times decrease, so does the margin in which signal artifacts can be accepted, which arises between the device under test and the test equipment itself.
One such specialized probe is the P7350, spun out of Tektronix early last year. This 5-GHz differential probe features just 0.3 pF of differential capacitance, 60 dB of common-mode rejection ratio (CMRR), and less than 100 ps of rise time. The announcement was made at last year's Spring Intel Developer Forum. Intel and others are preparing the high-speed silicon devices for future gigabit serial buses (Fig. 2a).
At last year's Winter Intel Developer Forum, Agilent Technologies introduced its E2969a Soft Touch probe with just 0.7 pF of capacitance loading. Even more recently, the company showed off the industry's first interposer analysis probe for testing next-generation double-data-rate 2 (DDR2) synchronous dynamic RAM (SDRAM) buses. The FSI60075 probe, developed jointly with FuturePlus Systems, enables the design and debugging of SDRAMs at 533 Mtransfers/s, using a standard JEDEC DDR2 dual-inline memory module (DIMM) (Fig. 2b).
Last month, Agilent unveiled a low-cost, high-performance 1.5-GHz differential probe for its Infiniium 54830 series of mixed-signal and digital storage oscilloscopes. The InfiniiMax 1130A makes differential measurements as well as single-ended measurements, all from a single probe amplifier. Included with the $3195 probe is an embedded resistor in its tip for impedance compensation.
FuturePlus Systems is constantly upgrading its probes, sometimes working jointly with other T&M equipment manufacturers. For example, its FS2240HT probe for HyperTransport systems embeds the tip resistor in the probe's small connector, instead of having the tip resistor on the target test board. The result is a more flexible probing approach for testing four-layer pc boards.
Agilent's Fall IDF probe announcement is but a small part of a major product portfolio announcement the company made at the conference for PCI Express. The announcement covered equipment, software, and services for PCI Express' physical layer, as well as system testing of protocol, transaction, and data-link layers (Fig. 3). Introduced was configuration and operating-system software for the transaction and protocol layers, and a demo of the products was provided. "This was the first time an X16 PCI Express implementation was demonstrated publicly," says Luciana Wingert, product manager for Agilent's Design Validation Division.
ADVANCING THE STATE OF MEASUREMENT ART
Advances are constantly being made in oscilloscopes, logic analyzers, and other instruments to handle the challenges of high-speed serial testing. For example, Tektronix recently introduced its 7-GHz TDS7704B digital phosphor oscilloscope (DPO). When coupled with the company's CSA7474B communication signal analyzer, the DPO raises the performance bar for measuring high-speed serial data buses. Key to the scope's performance is a silicon-germanium (SiGe) trigger system, which can measure jitter as low as 1.0 ps rms and detect glitches down to 110 ps. Tektronix also offers the RT-EYE serial data-compliance and analysis software. It works with the DPO and the P7450 probe to automate PCI Express compliance testing (Fig. 4).
"High-speed environments such as Fibre Channel, XAUI (extended attachment-unit interface), InfiniBand, and PCI Express present engineers with significant analysis and interoperability challenges," says Colin Shepard, Tektronix's vice president of oscilloscope products. "Our customers are looking for test equipment that can handle the raw performance of the latest buses, and equally important, make complex, time-consuming testing fast and simple."
LeCroy offers the 6-GHz 8620A digital storage oscilloscope (DSO) and the 6-GHz SDA 6020 6-GHz serial data analyzer. Both are four-channel instruments that provide real-time data/rate bandwidths to 20 Gsamples/s. Recently, LeCroy upgraded its 6-GHz SDA6000A, 5-GHz 5000A, and 3-GHz 3000A serial data analyzers to trigger on 2.7-Gbit/s bit streams (Fig. 5).
"Design engineers need an entire suite of tools to verify the performance of PCI Express systems, and Agilent Technologies has the total portfolio that enables them to work the wave of PCI Express technology," says Sandra Oberdorfer, marketing manager for System and Test Protocol at Agilent's Digital Verification Solutions Division. In many cases, an oscilloscope, logic analyzer, noise source, BER tester, time-domain reflectometer (TDR), and many other specialized instruments may be required to ascertain the signal integrity of a high-speed serial bus.
Logic analyzers, which are still vital to the development of high-speed serial buses, are always getting upgraded. In fact, design engineers often use an advanced logic analyzer for early design debugging, capturing raw data, and system-level debugging. Lately, however, they're leaning more on a relatively new type of analyzer—the protocol analyzer—to debug bus-related high-level software problems. These tools supersede logic analyzers due to their deeper memories, which can grapple with high-level debugging tasks.
One of the hottest areas in the T&M realm involves BERTs and time-interval analyzers (TIAs). Companies like Wavecrest and Noise Com, among others, produce high-end BERTs that allow designers to ascertain the integrity of their high-speed serial data. Wavecrest, in particular, makes the SIA3000 TIA that compiles and presents the histogram of the timing location of data transitions passing a voltage threshold.
A BERT combines in one instrument the capabilities of a low-jitter signal source, a fast oscilloscope, and analysis software. Not all BERTs are the same, though. They differ on the amount of flexibility when handling data rates and I/O configurations. One characteristic to look for in a BERT is a flexible pulse generator that can insert controlled amounts of jitter, leading to better jitter-tolerance analysis.
EDUCATING THE DESIGNER
So designers can gain a better understanding of high-speed serial bus testing, the T&M industry has taken a more "educational" approach. Many T&M companies provide regional and Web presentations regarding the latest technology advances impacting design engineers working on serial gigabit-per-second chip-, board-, and system-level designs. These companies feel that it's not enough to introduce advanced products for these designs, but also to educate designers on how to use them to sort and solve heretofore hidden and often unrecognized design problems.
On another front, it has become quite evident that teamwork is essential. As serial-bus data rates keep rising, T&M equipment suppliers find that they must work in concert with silicon IC suppliers, hardware manufacturers, and package designers to design the most suitable instruments for their jobs. The days of a T&M company designing a piece of test equipment, mostly on its own, and releasing it to the market are no longer adequate. Silicon is simply outrunning the ability of T&M equipment to verify silicon's performance.
The issue of signal integrity in the digital arena is now taking center stage as digital designs and RF communications rapidly merge. What's needed is a new understanding on how accurate measurements can close the loop between the design and simulation phases of a system.
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