One of the industry's most highly integrated transceiver chips, the nPower BBTX100, handles 10-Gbit/s data rates and supports Ethernet and Fibre Channel interfaces. A separate version of the chip, the BBTX102, provides an OC-192-compatible (Sonet/SDH) interface. The highly integrated design also reduces power consumption, enabling higher port densities on line cards and Internet routers.
The CMOS serial transceiver chips use several company patents to achieve the high data rates at a power consumption of about 1.5 W. Both achieve their performance thanks to a powerful on-chip equalizer that compensates for signal losses and increases the distance over which the transceivers can receive the high-speed 10-Gbit/s serial stream on FR-4 pc boards.
Since the BBTX100 and -102 each can replace separate transmit and re-ceive circuits, they can easily double the number of ports. But since the power is also lower, the number of ports can actually be quadrupled versus previous-generation devices while staying within the original power budget if the physical space permits double the number of chips. This higher port density increases the bandwidth in these systems by a factor of four and lets them move more data through the cramped equipment racks in central offices and data centers.
The nPower BBTX100 is the industry's first multiprotocol transceiver. It can be configured on-the-fly for either 10-Gbit/s Ethernet or 10-Gbit/s Fibre Channel interfaces. That makes it possible to design line cards and optical transponders that serve both interfaces.
Focused on OC-192 Sonet and synchronous digital hierarchy (SDH) interfaces, the nPower BBTX102 provides full-duplex 10-Gbit/s operation. Like the BBTX100, it replaces separate transmitter and receiver chips and consumes just one-fourth the power of the two-chip solution. The device receives the ultra-high-speed data (up to 10.7 Gbits/s for forward-error correction) from an OC-192 optical transceiver that extracts the data stream from a fiber-optic cable. The chip then performs extensive processing to convert the data into four lower-speed serial streams (up to 3.223 Gbits/s each). These streams are then delivered over an SFI-4.2 Phase 2 interface (serializer/deserializer Framer Interface Level-4.2, Phase 2).
The BBTX100 chip for 10-Gbit/s Ethernet and 10-Gbit/s Fibre Channel can receive a 10.3- to 10.6-Gbit/s data stream from an optical interface and convert it into four 3.125- to 3.18-Gbit/s output serial streams. The BBTX100 can be switched on-the-fly between protocols via an external pin.
Both chips are full duplex. The entire process is simultaneously repeated in the other direction as parallel data from the media-access control (MAC), network processor, or switch fabric is sent through the transceivers back to the fiber-optic transceiver. The receive function of both devices begins with the proprietary equalizer that compensates for signal losses. After recovering the 10-Gbit/s signal, a 64B/66B-gearbox descrambler feeds the data into a byte alignment unit. The data is then 8B/10B encoded and transmitted over four CML drivers.
A parallel loopback mode (transmitter to receiver) and a serial loopback (receiver to transmitter) are provided for diagnostic purposes. On-chip clock synthesis is performed by low-jitter phase-locked loops, which permit the use of a slower 156.25-MHz (for 10-Gbit Ethernet) or 159.375-MHz (10-Gbit Fibre Channel) clock reference.
Sampling now, production is slated for the fourth quarter. Both come in 192-contact BGA packages. Depending on space requirements, designers can order the devices in either a 12- by 12-mm or a 17- by 17-mm package. When housed in the 17-mm package, the BBTX100 sells for $250 apiece, and the BBTX102 goes for $280, both in lots of 10,000 units. Add $50 and $56, respectively, for the smaller 12-mm packages.
BitBlitz Communications Inc., www.bitblitz.com; (510) 656-4600, ext. 235.
