High-speed digital circuits need clean power, but can stress power systems in ways that make it difficult for the system to deliver what’s needed. For example, the current drawn by high-speed processors and FPGAs can change by tens of amperes in a nanosecond. The power system is expected to remain stable when this occurs, without ringing, over-shooting or under-shooting, or responding in any way that might cause the circuitry to misbehave.
Maintaining clean, regulated voltage requires more than a high-quality power supply. The power distribution network (PDN)—which, together with the power supply itself, form the power system—must maintain a low source impedance, with minimal resistance and well-controlled reactive elements.
Designers can validate impedance performance by measuring the impedance with a network analyzer.
Measuring The Power Supply’s Output Impedance
Ideally, a power supply should have a zero source impedance. (That is, “looking into” the power supply, the circuitry should “see” 0 Ω.) A low-impedance source helps keep noise and “junk” out of the circuitry and minimizes interaction among various sections of the circuit.
A regulated power supply is, in effect, an amplifier with feedback. The rules that apply to feedback-amplifier design also apply to regulated power supplies. One of these is that the regulation’s effectiveness varies with the magnitude and frequency of the load variations.
At “low” frequencies, the power system’s impedance is largely determined by the control loop of the voltage regulator, since it is lower than the impedance of the decoupling capacitors and board planes. At “high” frequencies, above the bandwidth of the voltage regulator, the system impedance is primarily controlled by the circuit board planes and decoupling capacitors as it is lower than the impedance of the voltage regulator.
The source impedance of the power system can be measured using a vector network analyzer (VNA). Getting an accurate reading depends on correctly connecting the probes and accounting for parasitics. The goal is to minimize the impedance between the two probe ports and the measurement impedance. Figure 1 shows the idealized connection. The signal and ground connections of Port 1 and port 2 each meet at a single point at the device under test (DUT).
A low-impedance system (a few ohms or less) is ideally measured using the two-port, shunt-through method.
Figure 2 shows a schematic representation of the measurement setup. Term1 and Term2 are the s-parameter ports representing Port 1 and Port 2 from Figure 1. Port 1 presents a source impedance of 50 Ω while Port 2 presents a load impedance of 50 Ω in parallel with the R_DUT. The analyzer measures the gain from Port 1 to Port 2. The resistance and inductance of the interconnecting wires are shown as L5-L8. The resistance of L6 and L8 are the dc resistance terms connecting ground leads.
These ground resistance elements form a dc ground loop. This can be seen in that the bottom of the R_DUT is not connected directly to ground, but is connected through the parallel impedance of L6 and L8, floating the R_DUT above ground. If this ground loop is not accounted for, the measured result will be the parallel impedance of L6 and L8 in addition to R_DUT.
The simplest way to eliminate the dc ground loop from the measurement is to insert a common-mode transformer (Fig. 1, again). The transformer must have wide bandwidth, low loss, and tight coupling. Otherwise, the results won’t be accurate over the measured frequency range. It’s also important to maintain the 50-Ω transmission-line impedance through this transformer. This is accomplished by using a precision coaxial wound transformer, such as the Picotest J2102A.
We can easily calculate the magnitude of this s-parameter measurement. For simplicity, we’ve omitted the imaginary terms for all three elements, R_DUT, RS and RL:
Solving for R_DUT:
As our measurements are in dB, it’s helpful, for the purposes of comparison to solve for S21 in dB:
We can evaluate the sensitivity of the R_DUT to RS, RL, and S21 by evaluating the first derivative of Equation 2 with respect to each variable:
dRL = –4.003 × 10–8 
dS21 = 25.02 
dRS = 2.001 × 10–4 
Note that, in this derivation, S21 is a magnitude and not in dB. The R_DUT impedance is approximately 25 × S21, as seen in dS21.
The common-mode transformer can be on the input or output side. In either location it increases the impedance between the port to which it’s connected and R_DUT. The sensitivity of the R_DUT measurement to the source impedance (dRS) is much greater than the sensitivity of the R_DUT measurement to the load (dRL) as seen in Equations 5 and 6. It’s preferable to place the common-mode transformer on the less-sensitive load side (Port 2), as shown in Figure 1.
The circuit in Figure 2 was simulated using the Agilent Advanced Design System simulator (ADS), which simulates s parameters that can be directly compared to the measurements. The results are in excellent agreement.
Z_DUT = –S21 • RS • RLS21 • RL + S21 • RS – 2 • RL 
The noise floor should be determined before making such measurements. Figure 3 shows the noise floor for this setup.
The –120-dB noise floor means it’s theoretically possible to measure impedances as low as 25 µΩ (as indicated by Equation 3). As there should be at least a 10-dB margin above the noise floor, a more practical limit is 80 µΩ.
The resistance of the device is calculated using Equation 3 as:
R_DUT(–82.5) = 1.89 × 10–3 
The slight impedance dip at 10 kHz is primarily due to the inductance of the leads connecting the resistor to the SMA connectors and the solder mount of the resistor itself. The inductance of the resistor can be calculated from the 10-MHz measured impedance, which is in the inductive region.
R_DUT(–59) = 0.028 
L_DUT=450 pH 
Carrying the measurement to its practical limit, we measured a 0.001-Ω resistor, using the same two-port method. To reduce board and cabling parasitics, we created a printed-circuit board (PCB) to mount the resistor along with two SMA connectors. SMA connectors were mounted at each end and the connecting traces sized at 113 mils to maintain a 50-Ω impedance from the analyzer right up to the resistor (Fig. 6).
The resistance of the device is again calculated using Equation 3 as:
R_DUT(–86.0) = 1.25 × 10–3 
Figure 6 shows the measured result.
It’s possible to measure very low power-system impedances using the two-port s-parameter shunt-through method if you incorporate a common-mode transformer to isolate the effects of test-lead resistance. Impedances as low as 1 mΩ and 450 pH have been successfully measured using this method.
- “Ultra-Low Impedance Measurements Using 2-Port Measurements,” Agilent 5989-5935EN
- “Evaluating DC-DC Converters and PDN with the E5061B LF-RF Network Analyzer,” Agilent 5990-5902EN
- “Measuring Milliohms and PicoHenrys in Power Distribution Networks,” Istvan Novak, DesignCon Feb 2000
- “Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency Range,” Istvan Novak, Yasuhiro Mori, Mike Resso, DesignCon 2010
- “On-Die Capacitance Measurements in the Frequency and Time Domains,” Larry D. Smith, Shishuang Sun, Mayra Sarmiento , Zhe Li, Karthik Chandrasekar, DesignCon 2011
- “An Accurate Method For Measuring Capacitor ESL,” Steve Sandler, How2Power, April 2011
- “DC Biased Impedance Measurement using the J2130,” OMICRON Lab, http://www.omicron-lab.com/fileadmin/assets/application_notes/App_Note_DC_Bias_Impedance_V1_0.pdf
- “Capacitor ESR Measurement,” OMICRON Lab, http://www.omicron-lab.com/fileadmin/assets/application_notes/App_Note_ESR_Measurement_V1_1.pdf