Electronic Design
IEEE 1149.7 Standard Improves JTAG Functionality

IEEE 1149.7 Standard Improves JTAG Functionality

In updating the well-known but dated IEEE 1149.1 JTAG test standard, the IEEE’s test and debug working group has maintained backward compatibility with the earlier standard while building in more robustness for the future. The new standard, IEEE 1149.7, enables test engineers to do more with less.

Approved in December and published in February, 1149.7 addresses the changes that have occurred in the decades since the old 1149.1 standard was approved. It also provides a foundation for future test and debug technologies. The 1149.7 standard is not intended to replace its predecessor, but rather use the old standard as a foundation, extending and improving upon it.

An important aspect of 1149.7 is its support for two-pin operation, which provides a gateway to future device architectures. The standard still supports the four-pin mode of 1149.1, which allows 1149.7-compatible testers to plug into 1149.1-based JTAG ports.

The 1149.1 standard was primarily aimed at providing capabilities for board test, helping to determine whether ICs were soldered properly to the board. In 1149.7, the tap controllers now found in just about all ICs can be used a bit more intelligently, says Stephen Lau, emulation technology manager at Texas Instruments. “At Texas Instruments, for example, we have lots of devices with test-access port (TAP) controllers inside them and the scan chains can get quite long,” says Lau.

This can make debug take far longer than it needs to. Thus, the 1149.7 standard can implement a chip-level series bypass that significantly improves debug performance. This bypass bit can be used to shorten scan chains in series topologies, making for faster debugging. It also can be used to create a “firewall” to protect system operation when a debug-and-test controller (DTC) is connected or disconnected from the test socket.

Yet another key addition to 1149.7 is the ability to perform background data transfers concurrently with advanced scan transactions. “The benefit of this is that we can overlay scan transactions for debug with instrumentation information,” says Lau. For example, imagine that you’re using JTAG to debug an ARM processor in a cell phone. “You can have it send the data stream back from the device to tell you how it’s operating,” says Lau. This capability of 1149.7, dubbed BDX, uses the two-pin port in a manner similar to a time-division multiplexing switch.

Whereas 1149.1 supported only series topologies, 1149.7 now also supports a star scan topology (see the figure). “Many modern ICs are based on stacked dies,” says Lau. “In a series topology, scanning stacked dies doesn’t work all that well due to the likelihood of crossed wires. With a star topology, things are much easier to hook up.” Another benefit here is the ability to remove test-data-input (TDI) and test-data-output (TDO) hookups in two-pin mode, resulting in fewer wire bonds in stacked-die arrangements.

The 1149.7 standard features six classes (T0 to T5) and includes 1149.1 extensions, ensuring compliance for chips with multiple TAPs. It also offers well-defined power control functions, including four selectable power modes.

IEEE Standards Association

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.