For most of its young life, the Universal Serial Bus, commonly known as USB, has been relegated to the slow lane. While designers have developed USB keyboards, mice, and 56k modems, high-speed peripherals have overpowered the current USB 1.1 bus. This is about to change. The recently released USB 2.0 standard boosts speeds up to 40 times faster than the previous USB 1.1 standard. This extends the reach of USB to hard-disk drives, cable modems, home networking products, and other kinds of fast peripherals.
With the USB 2.0 standard now in place, it isn't surprising to see companies developing chips to support it. One of these companies is Cypress Semiconductor, the market leader in USB controllers. It has developed a single-chip USB 2.0 solution called the EZ-USB FX2. This chip contains a USB 2.0 physical-layer (PHY) circuit and an 8051 microcontroller based on the company's EZ-USB FX architecture.
The company believes the single-chip EZ-USB FX2 has certain advantages for designers developing USB 2.0 peripherals in comparison to both the multichip and ASIC approaches. With a multichip solution, a designer basically purchases a USB 2.0 transceiver and serial interface engine (SIE), and interfaces the transceiver to a microprocessor. In this situation, that microprocessor deals with much of the USB protocol. With a single-chip approach, which is the one that Cypress is taking with the FX2, a designer can interface the chip directly to the peripheral application.
Of course, a designer can achieve the highest level of integration by building a system-on-a-chip ASIC and integrating all of the necessary parts onto it. But then, the designer is faced with doing the work for both the application and the USB 2.0. This means the design effort is higher and time-to-market is longer. The benefit of such an approach is that the cost of the final parts can be really low. For very high volumes, this approach is definitely worthwhile. Still, Cypress believes the sweet spot is the single-chip approach and this is the reason why the company built the USB 2.0 microcontroller.
Concerning time-to-market, the company says that all of the ASIC approaches it has ever seen usually required two design spins, because doing USB protocols is a difficult job. This level of difficulty is likely to increase at 480 Mbits/s, making it a little more risky when taking the ASIC approach, particularly regarding the time-to-market.
Cypress points out that interfacing between digital and analog has more nuances when running at 480 Mbits/s. There's a lot less noise tolerance, for instance. For one thing, the voltage swings in USB 2.0 are smaller than in USB 1.1. Creating a 100-kgate IC, for example, with the small PHY is going to present a greater challenge. The company claims it isn't going to be impossible, but it will certainly affect the time-to-market. In the company's opinion, the first ASICs will have to be spun twice, which is what will affect time-to-market.
Another point Cypress makes is that the USB 2.0 protocol requires a designer to perform the initial renumeration at the USB 1.1 "full-speed" rate (12 Mbits/s). In other words, the transceiver and SIE for USB 2.0 has to do both the full-speed and the high-speed rates. This means the design must be compatible with USB 1.1 as well as USB 2.0. Cypress thinks ready-made solutions are definitely going to have an advantage over solutions done from scratch.
A Fine-Tuning Should Help
Cypress believes its single-chip solution has given the company a chance to fine-tune the USB 2.0 architecture. This is a factor to consider when it comes to obtaining the high-performance I/O needed to keep up with the 480-Mbit/s USB 2.0 speed.
In addition, Cypress sees a problem with pin count in multichip solutions. In USB 1.1 devices, the data-path width was 8 bits. Now, with USB 2.0, the width is at least 32 bits for the data path. This can result in large packages, like 100- and 128-pin plastic quad flatpacks (PQFPs). According to the company, this is just for the SIE and PHYs. It doesn't include a microcontroller. The package can swamp the cost of the die. Therefore, the overall system cost can be higher.
Cypress has three versions of its chip, with the smallest a 56-pin small shrink outline package (SSOP). The reason for the low number of pins is that the wide data path is inside the chip. The package pins are for interfacing to the outside world.
In summary, the advantages of the single-chip approach can be thought of as performance, flexibility, and value. With the wide data buses inside the chip, the company can actually tune the architecture, as mentioned, to accommodate the high speed. One of the features of the FX2 part is the ability to use a low-cost microprocessor, the 8051, and still achieve very high performance. As for flexibility, programmable interfaces on the USB 2.0 part can be programmed to a specific application. Value comes from high integration and a low-pin-count package.
The FX2 features an 8-bit 8051 microprocessor core, which runs at 12, 24, or 48 MHz, depending on the application (Fig. 1). The reason the microprocessor has a wide range is to accommodate various power consumption and application needs and still maintain the high data rate of USB 2.0. In addition, the USB endpoint data buffer and slave FIFO are now one and the same FIFO. It connects directly to the Cypress Smart USB 2.0 SIE. As shown in the diagram, data can come into the transceiver, go through the SIE, and then move directly to the FIFO, which is accessible in the outside world through an 8- or 16-bit data path. Notice that there's no microprocessor in that data path.
Still, the microprocessor does have access to the FIFO. It can look at packet headers, for example, for Internet access applications. But, the speed of the data path is independent of how fast the processor is running. This is an example of the tuned architecture.
The Cypress Smart USB 2.0 SIE, like the company's previous FX part, implements most of the USB 2.0 protocol. Because this is the case, the designer doesn't have to worry about things like all three stages of a control transaction, nor does the microprocessor need to become involved. That is all handled by the Smart SIE.
Cypress says it's in a unique position. When a customer orders the company's development board and plugs it into a PC, the board works without having to write any code. This is due to the Smart SIE. Obviously, the board won't be tuned to the user's application, but there's no frustration involved in getting the part to work. USB transfers take place immediately.
One other job handled by the Smart SIE is the Cypress firmware downloading. The firmware is in RAM in the FX2, so it can be downloaded using USB through the SIE. The SIE can do the downloading while the processor is in reset. Because the USB 2.0 specification is brand new, problems are certain to be encountered. Downloading provides the designer an easy way to update the part if the specification changes. The company considers this to be a major advantage because it decreases risk and uncertainty, and it increases time-to-market advantages.
A key point about the endpoint FIFO is that it's implemented as a dual-port RAM. USB is a packet protocol, which sends a whole packet of data at once. In USB 2.0, those packets are 512 bytes. If a classic FIFO is used and a bad CRC occurs, all the data has to be flushed out because it's bad data. By implementing the FIFO as a RAM, it becomes more like a packet FIFO. The whole packet can be loaded into the dual-port memory. If the CRC is fine, that packet can be swapped from the USB domain to the I/O domain. To the outside world, it still looks like a FIFO. But instead of loading data one word or one byte at a time, a whole packet of data is loaded at once.
Another point about the endpoint FIFO is speed related. Because data is coming in very fast, double buffering—at the least—is necessary for the packets. Cypress has gone a step further by making this aspect of the device programmable. Endpoints can be double, triple, or quadruple buffered, depending on the amount of data or elasticity that's needed. For example, in a mass storage peripheral, data comes off a read channel at a high rate of speed, and then it's sent onto the USB while the read/write head is moving to the next track. Quadruple buffering is needed in order to make this work.
The designer doesn't really have to become involved in how this works. The part looks like a regular FIFO to the outside world. It has FIFO full flags, FIFO empty flags, and a programmable flag. The fact that it's a "quantum" FIFO (in the company's words) with packets swapped in and out is completely transparent.
The quantum FIFO concept has blocks of 256-by-16 dual-port RAM (Fig. 2). They sit on the USB side while data is loaded or unloaded from the USB. Then the data is swapped across the dotted line (Fig. 2, again) to the I/O system environment when the entire packet is deemed good. The 8051 also has access to this memory, which is used, for instance, for other packet protocols. An example is Ethernet, where a packet might need to be examined before it's shipped out to an application. The 8051 can look at header packets and process them as required.
What may not be obvious here can be studied through a comparison between USB 1.1 and 2.0. When USB 2.0 came along, it required some thought about how to implement the architecture. If Cypress had stayed with the original architecture, it may have included a FIFO on the I/O side and another for the endpoint buffers for USB. But because USB 2.0 is so fast, both of those buffers would have been huge and, thus, increased the cost of the device.
The quantum FIFO idea is an ingenious way to combine those functions so that a FIFO is seen by the outside world and an endpoint buffer is seen by the internal chip. In effect, these are one and the same. In the previous architecture, these were separate memories. As separate FIFOs, it was easy to keep them in different timing domains. Different timing domains are still necessary with this implementation—one for USB and one for the outside world I/O—but that's accomplished in a more intelligent way. In contrast, the designer of a multichip scenario would have to go back to the two-FIFO arrangement, and all of the costs associated with having two large buffers.
The flexibility of the FX2 is enhanced by the general programmable interface (GPIF), which is a programmable state machine. It can generate all the control signals, for example, for an ATAPI hard-disk drive, a Utopia interface for DSL, or an enhanced printer port (EPP) for printers. The key point is that the designer can address all of these different interfaces with the same part, without using any glue logic. This extends to microprocessors too, such as the PowerPC, and digital signal processors (DSPs), as well as PCMCIA devices. Each might have required a different part to be glueless and, thus, cost effective. The GPIF enables the FX2 to adjust for each of these interfaces.
Designers must program the GPIF, but Cypress provides a software tool to generate the appropriate interface. The designer doesn't have to figure out how the interface works. In addition, the company has reference designs to help in this area.
As mentioned earlier, the FX2 comes in three packages. One is the 56-pin SSOP, another is a 100-pin thin quad flat pack (TQFP), and the third is a 128-pin TQFP. The differences in pin count are due to the number of inputs and outputs. The 128-pin package is there just in case the designer has to use external data and address buses and more than 8 kbytes of RAM. This makes the architecture extensible and gives the designer a growth path. The focus for Cypress, though, is on the two smaller packages.
Price & Availability
Samples of the FX2 will be available early in the fourth quarter of this year. Pricing varies with package type and program memory size, but all family members will be priced under $10 for low production volumes. Development kits will be available as well in the fourth quarter for $495 each.
Cypress Semiconductor Corp., 3901 North First St., San Jose, CA 95134; phone (408) 943-2600; fax (408) 922-0833; www.cypress.com.