Electronic Design
Micro Mixes Hard USB With Soft Peripherals

Micro Mixes Hard USB With Soft Peripherals

XMOS adds a hard core USB interface to its latest micro and targets its soft peripherals on digital audio applications. The XS1-SUx family (Fig. 1) has one or more 700 MIPS, 8-thread XCore processors along with a USB 2.0 interface. The latter has an on-chip PHY.

XMOS first released a multicore XCore-based chip (see Multicore And Soft Peripherals Target Multimedia Applications) where all peripherals were implemented in software. Bit banging tends to be hard with standard cores but when you have 8 threads that are tightly linked to the hardware then soft peripherals become efficient and very flexible.

Figure 1. The XS1 XCore supports 8 threads with a hardware scheduling system.

Still, some interfaces tend to be more efficient when implemented in hardware. This is the case with USB especially since the PHY is a key part and something that cannot be emulated in software. Likewise, the 12-bit 1Msample/s ADC makes analog chores easier.

The ADC is a handy addition but it tends to be used for control and interface chores when the chip is supporting its initial target market, streaming digital audio. Interfaces I2S and SPDIF are serial digital interfaces and match the XCore architecture very well. The single core XS1-SU1 is capable of handling 4 inputs and 4 outputs simultaneously while retaining sufficient processing power to massage the digital streams. Add the USB Audio 2.0 standard and the XS1-SUx family is almost a perfect match to support this application area.

The XS1-SU1 is a single core version of the USB-enabled architecture and it is priced at $5. The dual core XS1-SU2 adds more processing power.

Although digital audio is the target market for the new family, the chips are really general purpose processors, now with a USB and ADC on-board. The chips retain the high speed, serial XLink interfaces that can connect multiple chips together. Arrays of the quad core versions, without USB support, have tackled computational chores.

There is also a matching, on-chip interprocess communication system that compliments the XLink support. This allows threads to be placed on different cores in a multicore system.

Each core maintains the state of 8 threads and implements a hardware scheduler that is tied to the I/O system. They have 64 Kbytes of RAM and 128 bytes are maintained in deep sleep mode. There is 8 Kbytes of OTP memory. Off-chip serial storage is normally used for development. It can also be used in production as well. The OTP locks in an application or provides storage for keys or other static data.

The system has a number of power modes and is designed for low power operation. It has an integrated a DC-DC power supply that delivers a 1V supply for the core. The chips are designed to be mounted on a 2 layer board with a minimum number of external components.

A number of hardware development platforms are available for XS1 chips. XMOS is now using their own chip to implement JTAG debugging for these development tools.

Software support includes an Eclipse-based IDE that runs on Windows, Linux and the Mac. The XC compiler supports C and C++. XMOS has its own assembler and linker. There is also a cycle-based simulator and debugging is handled by the GNU gdb debugger. Digital audio runtime support is also part of the mix.

Dealing with soft peripherals is interesting. I have used them with the XS1 as well as other platforms like Parallax's Propeller (see Parallax Propeller). Modifying existing peripherals and coming up with new ones is something that is not possible with most alternatives.

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