In every high-speed digital system, designers continually face the challenge of keeping digital switching noise and ringing to a minimum. These undesirable effects, resulting from fast-switching digital data streams and control signals, can make ones appear to be zeros, or zeros appear to be ones, mucking up the control and data signals and creating erroneous results.
Complex pc-board designs with lots of copper ground planes, resistive terminations of signal lines, and controlled-impedance wiring layouts have typically been the tools keeping undesired noise and ringing in check. But as chip pin counts go up, board layouts become more and more complex, forcing designers to use increasingly greater amounts of metal layers in the board, driving up pc-board cost. Additionally, resistive termination schemes eat up considerable board area, especially if several hundred pins per chip must be terminated.
Board area isn't the only concern, though. Resistive termination also consumes a significant amount of power, often tens of milliamps per pin, which drives up system power consumption. In portable systems, this reduces the time that the system can operate on batteries.
Tackling many of the negative issues with existing termination schemes, designers at California Micro Devices Corp. have developed a nonlinear active termination building block. Dubbed EZterm, this block is available in two forms. A block of intellectual property (IP) is one form, for use in a custom chip design. EZterm also is available as a multichannel standalone chip, the first version of which will include 16 terminators in one small surface-mount package—the PAC NLT101. In either case, the nonlinear active terminator could be the best cure for noise and ringing developed so far.
The basic EZterm circuit, which must be attached to each line to be terminated, can conceptually be represented by two MOS transistor pairs and a current source (Fig. 1a). This circuit function, represented by the symbol shown in Fig. 1b, can replace the typical on-chip active clamping schemes that employ diodes, like those used in many bipolar and biCMOS circuits.
Alternatively, the circuit could replace on-chip or off-chip Thévenin termination resistor dividers. Furthermore, the block doesn't impact initial signal amplitude because it's connected in parallel to the signal line rather than in series with it.
In the basic circuit, the p-channel active clamping transistor in the upper left section and its n-channel complement in the lower left work together to clamp the signal to the upper-voltage rail and the lower-voltage rail, respectively. The upper- and lower-right transistors and the current source serve as threshold reference devices. When sufficient current flows into the drain of the n-channel threshold reference device, the gate of the lower active clamping device is biased at about one threshold voltage (VT) of the n-channel transistor, plus a small amount of overdrive voltage necessary to sustain the current through the device.
When the signal overshoot on the transmission line dips below ground (as soon as the potential difference between the gate of the n-channel clamping transistor and its source exceeds the VT level), then the n-channel device starts to conduct to source current from its drain, which is connected to ground. That clamps the signal at about or slightly below the ground level. For signal swings that move toward and above the upper-rail voltage level, the n-channel device turns off and the p-channel device begins to turn on, and it clamps the signal at or slightly above the supply level.
To better understand how the EZterm circuit functions, let's take a quick refresher on termination and clamping. One commonly used approach in logic circuits, especially in the TTL era, was to employ two stacked diodes on an input (Fig. 2a). The diodes could limit the signal overshoot and undershoot that might damage the internal circuitry, or cause ones to be recognized as zeros or vice versa.
Several issues arise with this approach as power-supply and signal interface voltages go down and speeds go up. For starters, the diodes have a fixed junction voltage between 0.8 and 1.0 V, which can limit their effectiveness in low-voltage systems. Also, circuit speeds have outstripped the ability of diodes to switch fast enough. That has relegated diodes, which still appear in most MOS circuits, to mostly protect the circuit inputs against electrostatic discharge.
Alternatively, termination schemes could be all passive, employing a Thévenin resistive divider whose element values are adjusted to match the characteristics of the signal transmission line (Fig. 2b). Such a scheme is easy to implement, although two resistors are required per pin, and each termination divider continually draws some current—nominally tens of milliamps, reaching as much as 60 mA/pin, depending on the voltage and impedance.
The company also estimates that it costs most firms around two cents per component purchased, attached, tested, and so on, as part of the overall cost in a moderate-volume manufacturing process. Additionally, the resistors need to match transmission line characteristics, but those characteristics may not be known until after the system has been designed.
The EZterm concept addresses all of the negative issues. For one thing, it doesn't have the junction voltage drop as do the diode-based schemes. Instead, only the much-lower MOS transistor threshold voltage has to be accounted for. That lets the new approach work with much-smaller signal swings. A plot examining the current turn-on characteristics of the EZterm, as well as the diode clamp schemes, clearly shows the EZterm circuitry turning on at lower voltage levels and attacking the problem faster (Fig. 3).
The termination circuit can eliminate all of the resistors and the bias supply needed for resistive termination, thereby lowering system cost. Plus, it consumes little power—typically less than 1 mA per signal line—and it can be switched on and off by employing additional transition-detection circuitry to further lower power consumption.
Also, the circuitry occupies a miniscule amount of chip area when it's embedded in a chip—less than 4 square mils when fabricated with 0.5-µm design rules. That area is pretty much the same as a bonding pad. But it saves some area as the cell can replace the ESD protection circuitry too, at no extra cost. This is because ESD protection is included in the cell structure. So, using the EZterm cells has a negligible impact on chip area and power.
The nonlinear circuits can self-adjust to the use of connectors and sockets too, as well as the variable loading that they can create. For example, a high-speed memory bus able to accommodate multiple memory modules would vary its loading depending on the number of modules plugged in. Therefore, the circuit always provides the "perfect" impedance match for the system, eliminating potential noise and signal reflections.
To evaluate the performance of the termination scheme, a square wave was fed down a transmission line to a CMOS buffer containing the typical ESD protection diodes. The resulting ringing and noise was compared to a similar configuration that included the EZterm block inserted at the buffer's input. The diode-based results revealed a significant amount of overshoot and noise (Fig. 4a). A very clean signal was achieved with the EZterm circuit (Fig. 4b). The less noisy horizontal portions of the EZterm-clamped signal show the effect of leveraging the lower threshold voltage of the MOS devices—typically only tenths of a volt or so versus the 0.8- to 1.0-V for the diodes.
The EZterm circuit will be available in the form of a 16-channel standalone IC, the PAC NLT101. It will also be offered as a block of IP that can be licensed and then embedded in custom chip designs. The standalone chip provides dual-rail clamping—that is, clamping to both ground and power-supply rails—and bus termination independent of line impedance or loading conditions. In a typical application, four such chips could replace and outperform 64 conventional Schottky-diode pairs. The PAC NLT101 will be housed in a 24-lead QSOP surface-mount package, although the company is exploring the use of even smaller chip-scale packaging options.
The chip is targeted at 3.3-V (or lower) systems and has a maximum power dissipation of less than 0.9 W. In a 2.5-V system, the terminator will clamp voltage swings above VDD to 370 mV and below ground to 480 mV. In comparison, TTL diodes clamp the voltage swings above VDD to 840 mV, and below ground to 1200 mV.
As a block of IP, the EZterm circuit will be implemented in several forms. Designers will have available both a standard clamp termination block and a three-state-buffer implementation (Fig. 5). Initially, the company will offer the circuits using a generic 0.5-µm CMOS process. The processing needs, though, aren't very demanding, allowing other companies to rapidly port the IP to their own processes or to a foundry.
The company is considering additional circuit options as well. One could be a version including power-reducing circuitry that snoops the signal lines to look for bus activity. If no activity is detected, then the snoop circuitry will shut down the termination circuit to reduce power. An ideal use for such a block would be in circuits targeted at portable and other low-power applications.
Price & Availability
The PAC NLT101, when housed in a 24-lead plastic QSOP, will sell for about $1.00 each in lots of 100,000 units. Samples are immediately available. Several options are offered for the EZterm circuit when purchased as a block of IP. License fees for the IP can be arranged in a number of ways, depending on volume. But the most common agreement will include an up-front licensing fee and a small per-pin royalty. In addition, the company will offer a specially priced "early adopter" program as an incentive to initial licensees.
California Micro Devices Corp., 215 Topaz St., Milpitas, CA 95035-5430; Contact Peter McIntyre for business partnering and Jim Southerland for applications support at (408) 263-3214; www.calmicro.com.