The ability to place voice information on data networks allows many companies to streamline their telephony and data networks, combining them into a single network based on Internet Protocol (IP). For such networks to be possible, though, designers need building blocks that provide abundant signal-processing resources to handle the voice, video, and other multimedia content. To provide such a solution, VxTel Inc. has developed a family of application-specific signal and packet processors called Voice-stream and Voice-packet ASICs. To support the ASICs, the company also has written the firmware to run the chips and the higher-level software for the applications. Furthermore, VxTel has developed board-level designs that will let customers rapidly implement scalable, carrier-grade media transport systems.
The signal-processing solution developed by VxTel promises to solve some of the key aggregation issues in the new generations of classless superswitches. These systems consist of ultra-dense, fully scalable data-centric architectures that will be employed in public network switches. The VX-SP1000 algorithm processor is the first chip in a family of circuits that will let designers create systems capable of implementing OC-3/OC-12 interfaces on a single card. Such cards provide about four times the density of any competitive Voice-over-IP (VoIP) solution.
In a typical VoIP system today, a voice subsystem board might contain 16 to 32 general-purpose DSP chips, which enables each board to handle from 120 to 620 voice channels (depending on the DSP chip performance). A system processor (a general-purpose microprocessor) typically performs both control and voice-packet processing. The processor also controls the multiple DSP boards that execute the voice-processing algorithms. The microprocessor performs various control functions and manages packet-data movement to the switch fabric. By replacing the generic DSP chips on the voice subsystem boards with its VX-SP1000, VxTel expects to drastically reduce system complexity and improve channel density per board. This helps lower the cost per channel in VoIP systems (Fig. 1).
The control portion of the system, shown in the lower half of Figure 1, will typically consist of a host microprocessor for control, some custom logic implemented in an FPGA, and perhaps a network processor like the Intel IXP1200. But to simplify the control portion of the system and improve overall performance, the company's second product will be a voice-packet processor. This chip, the VX-PP2000, is expected to be released late in the fourth quarter. It will replace the custom logic and network processor, simplifying the overall system design and performing sophisticated voice quality-of-service management. It also helps aggregate channels and match the capabilities to the VS-SP1000, considerably simplifying the system and providing a highly scalable architecture.
Voice-processing algorithms are very compute intensive, and processing multiple voice channels on a single chip requires lots of throughput. For example, a standard G.711 PCM channel that runs at 64 kbits requires about 10 to 12 MIPS, while a G.728 LD-CELP 16-kbit/s algorithm needs roughly 40 to 42 MIPS. These performance numbers include 64-ms echo cancellation and telephony support functions, such as comfort noise generation and DTMF tone generation and detection. Therefore, if each channel has to accommodate the toughest solution, then a processor would have to concurrently handle multiple 42-MIPS algorithm instances. Even today's best generic DSP approaches can't readily handle more than six to eight such voice channels.
That's where the VX-SP1000 can take over. Its architecture is optimized for executing the voice-processing algorithms. Depending on the top clock frequency, it can handle from 192 channels of G.711 PCM traffic when clocked at 166 MHz to 240 channels at 233 MHz. Similarly for G.729A, a CS-ACELP standard that cuts the bit rate to 8 kbits/s for audio, the chip can handle 96 or 120 channels, respectively. In comparison, VxTel estimates that high-performance general-purpose DSP chips like the TI C5420 and C544x series, can deliver just 24 and 76 channels of G.711 codecs, or 10 and 32 channels of G.729A codecs. That's only one half to one tenth the number possible with the VX-SP1000.
The algorithm signal processor will deliver on average about five times the channel density of the best generic DSP chips. Plus, with the companion VX-PP2000 packet processor to manage the data, the chip set will provide a solution that can go from the time-division multiplexed (TDM) bus on the user side to the Utopia interface on the network fabric side. Thus, designers have an end-to-end solution that includes the silicon, the codec firmware, the application software, and the reference designs.
To process the large number of voice channels, the VX-SP1000 algorithm processor combines a large, 512-kword by 16-bit on-chip static RAM with a high-speed multichannel memory-movement engine and interrupt controller (an intelligent bus fabric controlled by a MIPS-class embedded processor), four signal-processing blocks, and many other system resources (Fig. 2). Each of the four signal-processing blocks consists of a proprietary DSP core, a scalable N-kword by 16-bit data memory, and an N-kword by 40-bit program memory. Word depths of the data and program memories will be optimized for each class of application to minimize chip area and power.
Additional on-chip resources include four full-duplex serial TDM channel interfaces, timers, a 32-bit expansion-port interface (VX-Bus), a dedicated VxTel control processor, and a JTAG/EJTAG test port. Every voice, facsimile, or data channel is implemented by a firmware module that's loaded into the program memory in each DSP core. The firmware executed by the DSP cores is independently configurable through the VxTel VX-SP1000 message protocol (VSMP) messaging system, which is typically running on the host control processor.
Capable of performing about 4 billion equivalent RISC instructions/s, each DSP core achieves that throughput by taking advantage of much parallelism and a 12-stage control pipeline. There are about 24 function units in the core that perform the computations. Part of the resources include eight 16-bit multipliers, 12 adders, three address generators, and one ALU. A 192-bit-wide bus ties the signal processor cores to the dual-ported data SRAMS in order to maximize data transfer speeds. With all four processor cores accessing the memory blocks, the bandwidth over the wide bus interfaces aggregates to 16 Gbytes/s (at 166-MHz).
At 166 MHz, the chip will consume about 2.5 W when a 1.8-V supply powers the core and the I/O is configured for 3.3-V operation. At that speed, the chip performs about 16 billion RISC operations/s to execute the voice-processing firmware. All of the memories necessary to hold the program, data, temporary data (buffers), and codebook tables are on the chip.
The multistage pipeline used in each DSP core helps ensure maximum throughput. Plus, the DSP core quartet provides a second level of parallelism to further improve throughput. Designers additionally plan on offering a 233-MHz version of the chip, which will boost throughput by 50%. The on-chip DSP blocks support the execution of many telephony coding standards—G.165/G.168 for echo cancellation, and G.729A, G.723.1, G.726/727, G.728, and G.711, as well as GSM-FR and EFR for various voice codecs. VxTel has developed the appropriate firmware, which can be downloaded to the chip at any time to support updated channel configuration requirements.
Furthermore, the chip can support silence suppression, along with voice-activity detection and comfort-noise-generation, which both help reduce bandwidth requirements and improve the quality of service. Also possible are fax and modem tone recognition, Group 3 facsimile capability, 2100-Hz tone disabling with phase reversal, and bad frame interpolation. The chip enables fast convergence on the voice-band echo canceller too, which helps deliver toll-grade voice quality.
The telephony-optimized features included on-chip consist of a PCM highway interface that permits up to 128 DS0 time slots per serial port and the four TDM serial ports. The relatively low power of the VX-SP1000 allows the use of multiple chips in an array of compute elements, thereby reducing the number of boards required, or considerably increasing the number of ports that the system can offer.
Although the first VX-SP1000 is optimized for VoIP systems, future implementations can be reoptimized to handle DSL and modem channels, and even wireless data transfers. The chip is part of a complete solution developed by VxTel that also includes the VX-PP2000 packet processor, the algorithm processor firmware, and the higher-level application-interface software.
Price & Availability
The VX-SP1000 is housed in a 256-contact BGA package and will be sampled next quarter. In 1000-unit quantities, the 166-MHz version sells for $650 per chip, including the firmware. An application software license costs $150,000.
VxTel Inc., 47224 Mission Falls Ct., Fremont, CA 94539; contact Vijay Parmar at (510) 979-2100; www.vxtel.com.