Electronic Design
SpringSoft Moves Toward Speeding Functional Closure

SpringSoft Moves Toward Speeding Functional Closure

A trio of announcements by SpringSoft unveils a strategy that’s aimed at getting more quickly to what the company terms “functional closure,” or a combination of hardware and software functional signoff. One announcement concerns comprehensive support for the Universal Verification Methodology (UVM) in the Verdi debug suite. The second involves enhancements to the Certitude functional qualification system. The third is a new product, the ProtoLink Probe Visualizer, which simplifies debug of FPGA-based prototyping boards.

On the Verdi front, SpringSoft’s addition of support for UVM signals the growing industry momentum of this verification standard. Built atop the foundation of IEEE-1800 SystemVerilog, UVM is being well established as an industry-standard approach to ensuring that testbench code (or verification IP) is reusable and interoperable, even if it’s integrated from multiple sources or developed in different methodologies. Verdi now adds UVM source code and new transaction-recording capabilities to its existing HDL debug platform. As a result, it’s easier for designers to visualize the behavior of their system designs over time.

Verdi now automatically records all UVM transactions in the SpringSoft Fast Signal Database (FSDB), which is where Verdi stores results from verification tools. The result is a complete record of the traffic between testbench components. That transaction data can be used within the existing Verdi waveform tool or it can be exported to a new UML-based (Unified Modeling Language) sequence diagram view. There is no longer any need for manual recording processes to keep track of transactions.

Certitude is SpringSoft’s tool for confirming that the implementation of a chip design functions as specified. What’s important about a tool such as Certitude is its ability to objectively measure the overall effectiveness of the verification environment. Traditional means of measuring coverage are insufficient these days. Certitude’s approach is to methodically introduce bugs into the design and then measure the testbench’s ability to find them (see the figure).

Improvements to Certitude have been made in several areas. For one, there is improved support for system-on-a-chip (SoC) qualification, with new fault types added to better represent typical SoC failures in connectivity between functional blocks. For another, “noise” has been eliminated in the tool’s output by implementing expanded fault dropping to remove redundancy in the results. Finally, the tool now guides users by ranking results based on “fault impact,” giving them a clue as to which results are most likely to bear fruit if looked at more closely.

Many designers opt to use FPGA prototype boards for register transfer level (RTL) verification. Whether these boards are purpose-built from scratch or a commercial product, they can be a bear to set up and debug. That’s time taken away from shaking out the design that the board itself is meant to debug.

SpringSoft’s ProtoLink Probe Visualizer is a means of increasing visibility into that FPGA board’s design. The product is a combination of hardware, software, and specialized IP that enables designers to probe large numbers of signals over many cycles on their prototype boards. Waveforms can be viewed across multiple FPGAs to better analyze design behavior.

The hardware part of the product, the ProtoLink hardware interface kit, includes the ProtoLink interface card, which bridges the workstation running the Probe Visualizer software to the prototype board via standard J-connectors or Mictor connectors. A fast probe-ECO (engineering change order) flow enables probes to be quickly added or changed. The card carries 2 Gbytes of probe memory to store probe data. The interface card and workstation are linked by a high-speed Fibre channel connection. The system supports both custom prototype boards as well as pre-fabricated boards (HAPS, TAI Logic Modules, and ChipIT).


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