With 0.13-µm processes coming online and 0.10-µm processes waiting in the wings, the stage is set for ASIC and system-on-a-chip (SoC) designs to grow exponentially larger and more complex. Such designs are outstripping the capacity of today's verification systems, creating a bottleneck in the design process that can delay or even prevent getting end products to market.
Verification of IC designs at the system level is more complicated and difficult than ever. These designs can't be exercised fully unless the design team's verification system can run actual application code on them. If the design team doesn't have a verification system with enormous capacity at its disposal, this process can take a very long time, if it's possible at all. In addition, the designers typically must run multiple iterations of the verification process. Again, the lack of capacity can be a killer. The resulting "verification gap" is quickly attaining status as Public Enemy No. 1 in the IC design community.
Quickturn's CoBALT Ultra design verification system directly addresses this need, offering massive capacity of more than 100 million ASIC gates and 64 Gbytes of memory (Fig. 1). The single-chassis system accommodates even the largest chip and system designs, while providing the engineer with a full set of tools that includes simulation acceleration, synthesizable test bench acceleration, and in-circuit emulation.
CoBALT Ultra is the latest member of Quickturn's Concurrent Broadcast Array Logic Technology (CoBALT) family. It sports dramatic gains in functionality compared to its predecessor, the CoBALT Plus. Using a massive array of newly designed custom emulation ASICs, the Ultra delivers more than five times the capacity and double the runtime performance of the older system. The concurrent processors are built on IBM's 0.12-µm, seven-layer copper process technology. (It's not entirely accidental that the initials for CoBALT Ultra comprise the chemical symbol for copper.)
The system can be scaled to support up to 112 million ASIC gates with an architecture that maintains constant in-circuit performance, even as designs grow to encompass multiple system boards. Thus, designer productivity is maintained as designs expand.
The CoBALT Ultra system isn't a followup to Quickturn's earlier CoBALT Plus system, but rather to its recently announced Palladium system, which has a capacity that can be expanded up to 16 million gates. This is more than adequate for the high-end, mainstream IC designs done today, as well as for those done in the near future. Meanwhile, the CoBALT Ultra system stands ready to serve the system-level verification needs of extremely high-end designs, offering the gate-count and memory headroom needed to do the job for quite some time to come. Both systems share the same fundamental silicon technology, and both represent a dramatic departure from FPGA-based simulation acceleration and emulation (Fig. 2).
A scalable architecture allows designers to use the system's entire capacity without negatively affecting runtime performance. RTL-to-verification time averages more than 4 million gates per hour using only a single workstation. Debugging designs of 10 million gates or more requires such RTL compile speed. As a result, full compiles of small designs, as well as incremental compiles of large designs (probe compiles) can be completed in minutes. This combination of fast compile times and minimal computer resource requirements lets designers turn entire designs several times in one day without tying up multiple computers.
"The fact is that SoCs are finally becoming real for a lot of designers," says Mike Butts, Cadence Fellow, a co-inventor of logic emulation and a key member of Cadence's Systems Solutions Business Unit. "To exercise an SoC properly, you need to boot the real-time operating system and run some real data on the application. The data sizes are very large, too, and take lots of cycles."
This level of verification is very difficult to do purely in software. It takes hardware acceleration. Another key aspect of the overall task is how the verification load is broken up. "When software is involved, you typically have a single thread of execution on which you need to run millions of cycles," Butts says. In many cases, particularly when verification loads involve regression testing or other similar tasks, the job can be handled nicely with a compute farm of PCs or workstations. A given test might comprise between 1000 and 10,000 cycles in such situations.
But when it comes to actually running software on a design, that single thread of execution must run for millions of cycles. "A farm won't do you any good, because it's only going to run on one machine," Butts explains. "One machine with a conventional simulator will take quite a long time. It might take weeks just to get the system booted."
The Palladium and CoBALT Ultra systems were designed with engineers running software on their designs in mind. This way, they get the kind of performance necessary to run millions of cycles of an execution thread, several times in a given workday.
Quickturn's previous generations of simulation acceleration/emulation hardware, such as the Mercury family, were based on FPGAs. The custom concurrent processors in the new systems deliver faster compile times and easier compile runs. "Because it's a processor, everything the machine does at runtime is discrete. It's all done in cycles, which are scheduled by a compiler," Butts says. "Essentially, it's like a processor with a million- or multimillion-bit wide instructions and many tens of thousands of register files. That can all be scheduled at compile time in a very predictable and very digital way, if you will."
Generally, FPGA-based acceleration architectures offer faster runtimes than one would anticipate from a processor-based architecture. But Quickturn's benchmarks of the Palladium/CoBALT Ultra architecture have been a pleasant surprise. Runtimes on the new systems are on a par with, if not slightly better than, the runtimes seen on the older FPGA-based systems. For highly asynchronous designs, however, the Mercury Plus system may still be the best bet.
An updated software environment is part of the CoBALT Ultra package. The environment brings the key features from Quickturn's earlier powerSuite together with Quest II packages for the CoBALT Plus machines. All functions, from RTL import through simulation acceleration, cosimulation, and in-circuit emulation, are controlled from one easy to use GUI.
Included is a compile flow supporting automatic batch processing like that of many simulators. Also offered is a debug environment with a waveform display tool, schematic viewer, design browser, and source-code browser. The drag-and-drop capability among these windows simplifies debugging.
Designers can initialize their memory or specific nets in their designs with debugging capabilities that let them get, set, force, and release values of internal nodes. In addition, "what if" scenarios are possible when a target system is connected in the in-circuit emulation tracer mode by changing the behavior of the control signals. Checkpoint/restart during simulation/emulation runs endows the CoBALT Ultra system with simulation-like capabilities.
Between the system's powerful architecture and new software, designers have a wide palette of verification options and modes available. The multiple modes of operation take users throughout the design cycle, from early RTL debugging to system-level hardware and software verification (Fig. 3).
The system's in-circuit emulation logic-analyzer function gives users a physical model of the silicon in development, as well as a comprehensive integrated logic debugging environment. This enables users to debug hardware and software in full system context with real external stimuli.
The ICE-Tracer mode offers debug capabilities that traditionally were found only in simulation. Designers can start, stop, examine, change memory, and even single-step an emulation run, all on-the-fly.
On the simulation acceleration side of the picture, the system provides several modes with varying levels of performance over and above simulation on its own. The first level is accelerated cosimulation with behavioral or C/C++ test benches. By using an existing test bench environment in this cycle-accurate cosimulation mode, users can accelerate simulation performance to speeds between 10 and 100 times faster than simulation alone. The easiest mode to implement, it removes all synthesizable RTL from the design under test and runs it on the accelerator. Simultaneously, the nonsynthesizable portions run on the workstation. The drawback here is that performance is limited by the speed of the workstation and its communication link with the accelerator.
A benefit of the cycle-accurate cosimulation mode is that it facilitates easy migration to in-circuit emulation. The CoBALT Ultra system can be directly linked with Solaris or RS6000 workstations by plugging a Direct Attached Stimulus (DAS) card into the workstation's PCI slot. Q/Bridge interfaces permit use of popular simulation environments in the test bench cosimulation mode with DAS cards at faster speeds. Designers can run their behavioral test bench by employing such tools as Leapfrog, ModelSim, NC-Verilog, SpeedSim, Vera, and Verilog-XL, and accelerate their original simulation environment by up to 50 times.
The next level of improvement in simulation acceleration is an accelerated transaction-based cosimulation mode. This new mode is typically 10 times faster than the cycle-accurate mode. It decouples the workstation and accelerator clocks and replaces serial data clocking with a high-level transactor. It also addresses the bottleneck imposed by the link between the workstation and accelerator, which limits performance due to the frequency and latency of communication between the design under test and the test bench running on the workstation. The transaction-based interface optimizes traffic and minimizes channel latency.
CoBALT Ultra's fastest simulation acceleration mode is the synthesizable test bench mode. In this mode, the designer's test bench and design are synthesized together to deliver performance an order of magnitude faster than accelerated cosimulation. Simulations run at the same speed as in-circuit emulation, providing extremely high performance in a targetless system. Designers can boost simulation runtime performance by 1000 to 100,000 times to speeds of 600 kHz. Here, all code is running at the speed of the accelerator, completely removing the bottlenecks imposed by the workstation and communication between it and the verification system. But it requires that users supply a synthesizable test bench, something few verification users are creating at this time.
A vector debug mode lets users run their original sign-off suite of vectors at high speeds. This mode is used for regression testing of sign-off vectors or for debugging the emulation model during the bring-up process.
A vector regression mode is available too, in which users can quickly and easily verify design changes. Whether they use pregenerated test vectors or vectors generated on-the-fly by C/C++ programs, designers will find vector regression a valuable function for final certification of any design before tapeout.
Another huge benefit of the CoBALT Ultra system is its multiuser capabilities. Up to 100 engineers can run any combination of simulation-acceleration and in-circuit emulation jobs at once.
Price & Availability
The CoBALT Ultra design verification system is priced according to configuration. An entry-level system with a minimum 7 million-gate configuration costs $5.6 million. Systems are available now with support for the IBM-AIX and Sun Solaris platforms. The system is available through QuickCycles as well, a turnkey program that provides access to Quickturn's verification environments on a per-project basis.
Quickturn, a Cadence company, 55 W. Trimble Rd., San Jose, CA 95131; (408) 914-6000; www.quickturn.com.