Electronic Design

Transmit-Path DACs For Portables Shrink Power Demand While Adding Features

The AD970x series of transmitpath digital-to-analog converters (DACs) for portables maintains compatibility with prior generations of Analog Devices' TxDAC series while reducing power dissipation and adding an on-chip voltage reference and RSET and RLOAD resistors. Clocking up to 175 Msamples/s, the series includes the 14-bit AD9707, the 12-bit AD9706, the 10-bit AD9705, and the 8-bit AD9704.

Thin-scaled small-outline package (TSSOP) versions are pin-compatible with the previous three generations of TxDAC devices. But a new package option for the 14-bit device sacrifices backward pin compatibility for for a host of new features. These include clock calibration for enhanced integral nonlinearity (INL) and differential nonlinearity (DNL).

Additionally, the smaller package's serial-peripheral-interface (SPI) connection provides microprocessor control of power-down functions. This version of the device also can reset the output common-mode voltage via a pin, making it possible to directly interface its output to components requiring common-mode levels above 0 V.

Power-wise, the AD9707 dissipates 24 mW with a 25-Msample/s clock and 2.5-MHz output frequency when it's running from 3.3 V and driving 2 mA. (Drive can be as high as 5 mA. Output current is set via an external resistor.) Dropping the operating voltage to 1.8 V and the output to 1 mA cuts power dissipation to 8 mW with a maximum 80-Msample clock rate. The most similar chip in the previous TxDAC generation—ADI's 14-bit, 210-Msample/s AD9744—consumes a hefty 135 mW.

Typical INL and DNL values at 3.3 V are ±3 and ±1.5 LSB respectively before calibration and ±0.8 and ±0.7 LSB after. Spurious free dynamic range (SFDR) to Nyquist ranges from 82 dBc with a 10-Msample/s clock and 1-MHz output to 78 dBc with a 175-Msample/s clock and 20-MHz output (or 75 dBc at 175 Msamples and 40 MHz). Total harmonic distortion (THD) is -78 dBc up to a 125-Msample/s clock with 2-MHz output. Signal-to-noise ratio (SNR) ranges from 82 dB with a 65-Msample/s clock and 5 MHz out to 70 dB at 175 Msamples and 5 MHz.

At 1.8 V and driving 1 mA, post-calibration DNL drops to ±0.5 LSB. Other values stay the same. Also at 1.8 V, SFDR to Nyquist ranges from 79 dBc with a 10-Msample/s clock and 1-MHz output to 71 dBc with an 80-Msample/s clock and 15-MHz output at 15 MHz (or 63 dBc at 80 Msamples/s and 30 MHz).

At the lower operating voltage and output, THD is a stillrespectable -79 dBc with a 10-Msample/s clock and 1-MHz output and -75 dBc on up to 65 Msamples/s and 2-MHz output. SNR ranges from 76 dB with a 25-Msample/s clock and 5 MHz out to 70 dB at 65 Msamples/s and 5 MHz.

These TxDACs will be in volume production next month. Thousand-unit pricing ranges from $5.75 to $2.75. An evaluation board is available. So are an integrated development and debugging software environment as well as a software pattern generator for driving the evaluation board.

See the figure

Analog Devices

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