Electronic Design

What's Hot At DAC

New tools and methodologies to be unveiled span system-level design to post-layout analysis.

As always, the 40th Design Automation Conference (DAC) in Anaheim (June 2-6) will have something for everyone concerned with EDA. The latest and greatest tools and methodologies will be displayed either on the show floor or in the sprawling labyrinth of high-walled demo suites. In addition, there's a full slate of technical sessions, panels, tutorials, and workshops to bring you up to date on the state of the art in design automation (see "Scanning The Sessions," p. 49). Also, the innumerable dinners, parties, and assorted gatherings provide ample opportunity to peer into the minds of the EDA industry's leading lights in an effort to discern key trends.

But as always, the tools are the stars of the show. DAC has long been the premier venue for EDA product rollouts. This year, attendees will see numerous announcements related to all areas of EDA: system-level design, intellectual-property (IP) and reuse/integration issues, pc-board tools, logic design, physical design, and analysis and verification.

A move up in abstraction has been in the offing for logical design for some time. We'll see some new developments in system-level design at the show, as tool flows continue to take shape for algorithmic design exploration.

According to Guy Moshe, president and CEO of Summit Design, C/C++ is the "common denominator" bridging SystemC and SystemVerilog, two of the leading candidates for system-level language supremacy. "C/C++ delivers the language abstraction with all its associated benefits, and the linkage to software with all the associated legacy and popularity," Moshe says.

For system-level design to work, there must be tools that provide viable hardware models to software developers early in the design cycle. Tenison EDA will show version 2 of its VTOC virtual silicon modeling tool, which converts Verilog code into C, C++, or SystemC. A new command-line feature gives users flexibility to build models of partial and incomplete designs, permitting coding of software or firmware even earlier in the development cycle.

Celoxica will show version 2 of its DK design suite, which performs what's called "software-compiled" system design. The tool uses high-level design languages to drive design verification and implementation. Also at DAC, Celoxica will demonstrate numerous applications and announce significant relationships with several IC companies, including ARM Ltd.

Although interest in SystemC is rising, many designers still require training in its application. Forte Design Systems will demonstrate online SystemC training, which will be offered free of charge from its Web site, www.forteds.com.

Another key to the viability of system-level design is a view into all aspects of design from the architectural level. In the latest version of its system-level power-estimation tool, ChipVision will include a new SystemC front end to supplement existing C/C++ support as well as source-code reverse-analysis capabilities. Called Orinoco 2003.1, the tool features a new scheduling graph that gives designers a view of their system architecture. Pricing is $120,000 for a three-year license.

System-level design has lagged somewhat in the practical realm. This is not due to a lack of design tools but rather the lack of a true system-level verification methodology in which hardware and software are verified concurrently. At DAC, Axis Systems will introduce such a methodology, one that can bind pre-built design and verification components together to raise abstraction levels from the front end to the back end of the cycle.

Meanwhile, CoWare will show its ConvergenSC product family, touted as the first system-level tools to use a common infrastructure for both design and verification. Built expressly for SystemC, ConvergenSC will launch its first product, System Designer, at the show. It provides high-speed simulation, architecture analysis, and design implementation on a single SystemC-based infrastructure. Capabilities include creation of SystemC transactional prototype models for systems-on-a-chip (SoCs) containing multiple processors, complex buses, memories, custom logic, and software.

System Designer's SystemC simulation architecture runs five times faster than the Open SystemC Initiative's reference simulator. Thanks to the tool's analysis capabilities, it can create optimal design architectures, including Bus Views, Memory Views, and Embedded Processor Views (Fig. 1). Transactional bus simulators are available to provide baseline configurations of popular bus standards like ARM's AMBA. Also, third-party tool support is available from Novas, Cadence, and Synopsys. Pricing starts at $105,000 for a three-year license.

Even though we can't shake the habit of referring to "front end" (logical design) and "back end" (physical design), the distinction is becoming less clear. Issues traditionally dealt with in the back end are being dragged further into the earlier portions of the design cycle.

Such trends are exemplified by tools like Atrenta's SpyGlass Low Power, which leverages the company's fast-synthesis engine to help designers create power-efficient RTL code early in the design cycle. It provides guidance for low-power techniques that target dynamic power, leakage power, and voltage-management issues. The tool identifies good active net candidates for clock gating, a technique that can save a lot of power.

Also aimed at RTL designers is InTime's RTL static timing-analysis methodology and RTL floorplanning products. InTime will demonstrate TimePlanner, its RTL planning system; TimeBuilder, its hierarchical, gate-level chip assembly floorplanner; and the new TimeDesigner tool, which allows RTL designers to visualize and solve timing issues directly from their RTL design environment.

The links between logical and physical design demand tools that can evaluate and improve the quality of RTL code before physical design ensues. Magma Design Automation's Blast Create 4.0 enables designers to synthesize and visualize their code, design constraints, testability requirements, and floorplan. It integrates fast high-capacity synthesis, silicon-virtual-prototyping (SVP) capabilities, full and incremental static timing analysis, design-for-test analysis and synthesis, and power analysis.

Blast Create doesn't rely on conventional wireload models or inaccurate physical design data. It can build and analyze a flat, multimillion-gate SVP that allows problems to be isolated and repaired in RTL. Pricing starts at $225,000/year for a three-year time-based license.

Synthesis technology is slowly evolving to meet next-generation design needs. At DAC, Synplicity will unveil its plans for a new class of ASIC physical synthesis technology that purports to bring the best of physical synthesis and SVP into one tool environment. The hope is that such a tool would address the needs of both the gate-level netlist handoff market, in which designers hand their work off to either internal or external organizations for physical design, and the emerging structured ASIC market. So-called structured ASICs are chips in which the underlying pattern of logic cells, memory, third-party intellectual property, and I/O are created ahead of time and customized by the application of the final few metal layers. Synplicity will also announce its development of physical synthesis software for LSI Logic's RapidChip architecture.

Synplicity's new technology will leverage its core synthesis algorithms as well as newly developed placement, routing, and automatic initial floorplanning technology. The resulting tool will be able to generate a final netlist and placement with high correlation to the final GDSII implementation of the design.

The search goes on for efficiency in analog design, an area notorious for painstaking handiwork. To that end, Sagantec's Anaconda is a schematic-driven, constraint-based compaction tool intended to target the significant manual effort involved in analog design reuse.

Reusing analog design elements takes a great deal of effort. It ranges from correctly sizing and placing the layout details of the many derivatives and variations of a given physical topology to circuit migration and to new processes. Anaconda provides an automated alternative to hand-layout of each derivative. It reads sizes and constraints from a schematic and then refines a given topology to automatically and accurately implement the specifications. Time-based licensing starts at $55,000/year.

Analog Design Automation will unveil a partnership program that pairs its Genius line of analog front-end tools with leading physical design tools, all within the customers' chosen design flow. Partners include Cadence, Ciranova, Mentor Graphics, Sagantec, Silicon Canvas, and Synopsys.

Right at the outset of a chip-design cycle, process shrinks can make settling on a cell library a daunting challenge. Libraries typically have over 700,000 data points, making manual comparisons between them untenable. A tool from startup Z Circuit Automation claims to simplify the task. The Z Circuit Library Analyzer compares entire libraries or cells within libraries for setup-and-hold times, area, delay, and power consumption for the set of conditions under which a given design will operate. Pricing starts at $5000 for a three-month subscription to a secure, real-time, Web-based server.

Designers of pc-boards will be interested in Multicap 7 and Multisim 7, the latest versions of Electronics Workbench's schematic capture and simulation tools for pc-board design. For those performing schematic entry without simulation, Multicap 7 performs pure schematic entry, drives simulation, and/or feeds pc-board layout. It offers model-less operation, eliminating the need to switch between part placement and wiring modes; autowiring (just click on two pins and the tool automatically creates a connection); and more.

With the Multisim 7 Spice simulator, users can verify circuits and correct errors before they appear in later design stages. It includes an integrated version of Multicap, allowing users to create and then instantly simulate circuit designs. Design-tool portfolios start at about $4000.

The increasing incidence of nanometer-scale ICs on pc boards means a corresponding increase in the number of differential signaling pairs on the boards themselves. Cadence will demonstrate a new design environment for implementing multi-gigabit serial interfaces in high-speed pc boards. The simulation-driven environment enables reductions in design time by allowing users to develop a comprehensive set of rules within the tool's constraint manager, then drive layout and routing with those rules. As a result, many iterative cycles between layout, simulation, and repair can be eliminated.

SynaptiCAD will show its new Debugger Pro, a remote VHDL and Verilog debugger, and a new version of TestBencher Pro, a graphical HDL model generator. With these two tightly integrated tools, designers can describe interface models using graphical timing diagrams, generate the code, and simulate and debug without ever leaving the design environment. Features include multiple waveform display windows, intuitive model development, and the ability to enable remote debugging across a network, even when the simulator and debugger run under different operating systems.

Augmenting its existing RTL-to-GDSII flow, Magma will show its new Blast Rail product for power integrity in nanometer IC designs. The tool simplifies power-rail design by combining power planning, power analysis, voltage-drop analysis, voltage-drop-induced delay analysis, and analysis of electromigration on rail wires and vias. Built with Magma's unified data model architecture, Blast Rail offers instant access to analysis data for on-the-fly corrections that avoid post-route iterations.

As IC manufacturing technology continues its march into the nanometer realm, so goes the cost of IC manufacturing. Current predictions have the cost of a mask set at 90 nm rising to $2 million. The cost of computing infrastructure capable of designing and verifying ICs is rising significantly as well. Mentor Graphics will roll out Calibre MTFlex, a next-generation extension to Calibre's current hierarchical data-processing engine (Fig. 2). The extension will enable the design-to-silicon tool suite to perform highly scalable, multi-threaded data processing in price-conscious distributed compute environments.

As always, design verification will be a hot topic at DAC. Assertion-based verification will be among the major trends emerging at the show. Assertions express expected design behavior and drive the emerging verification tools that use them to improve the quality of design validation. Driven by increasing complexity, assertion standards are shaping up, largely due to the efforts of Accellera. Formal-verification tools are improving as well. Some simulators now support assertions, giving designers even more reason to at least look into using them.

Novas will demonstrate the latest version of its Verdi behavior-based debug system with support for assertions. Assertions accelerate the ability of the debugging process to locate and isolate the causes for design behavior. Browsing and tracing tools are used to apply familiar debug techniques to assertions, allowing users to view assertion source code annotated with values produced by simulators and formal tools. They can also trace from assertion source directly to the HDL source code. Results of assertion evaluations can be seen in a waveform display, including trigger times and pass/fail results.

On the formal verification front, Real Intent will show version 4.0 of its Verix formal tool. Verix 4.0 delivers multimillion-gate capacity for formal assertion verification. It includes over 14 classes of automatic assertions, as well as a Verilog/VHDL-like assertion language that permits users to define their own assertions with a minimal learning curve.

The tool supports Accellera Open Verification Library (OVL) assertions, allowing users to apply formal analysis to verify behaviors expressed in OVL. Designers can plug-and-play OVL assertions between Verix and a simulator to perform formal and dynamic analysis (Fig. 3).

Putting the "formal" in formal verification, of course, is the notion of an exhaustive analysis of all possible test vectors. At DAC, 0-In Design Automation will announce the industry's first formal-verification metric that links simulation with formal-verification effectiveness. The result is a comprehensive measure of how well designers have verified their ASICs, SoCs, and custom ICs. With the unified metric, users will be able to identify verification holes in both simulation and formal verification. The metric highlights parts of the design that haven't received sufficient functional coverage in the context of a verification test plan.

Hardware-verification systems have sorely needed a capacity boost. Emulation and Verification Engineering (EVE) is debuting a multiboard system that extends the capacity of designs to 12 million ASIC-equivalent gates from 1.5 million gates in the previous version. The ZeBu platform accelerates the verification process of FPGA-based designs as well as the software-development cycle for embedded systems. Up to eight ZeBu boards can be connected together to accommodate designs ranging from 1 million to 12 million ASIC-equivalent gates. Thanks to EVE's Z-EmuNet networking technology, multiple boards can be installed in multiple PCs for use collectively on one large design or individually and concurrently on smaller designs. Pricing starts at $49,000 for a 1 million-gate system.

Need More Information?

Analog Design Automation


Axis Systems

Cadence Design Systems





Electronics Workbench


Forte Design Systems

InTime Software

Magma Design Automation

Mentor Graphics

Novas Software

OpenAccess Coalition

Open SystemC Initiative

Real Intent


Summit Design




Tenison EDA

Z Circuit Automation

0-In Design Automation

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