Electronic Design

3-Gbit/s Mux/Demux Takes On Next-Gen SAS Systems

Who would've thought serial would dominate the bus world? Parallel buses just couldn't keep up at distances over a few inches. Serial has won, and it's pushing into disk storage.

This is possible with chips like PMC-Sierra's QuadSMX 3G, designed to implement the recently approved Serial Attached SCSI (SAS) industry standard for storage systems and hard-disk drive interfaces. SAS enables the migration of SCSI-based systems to gigabit-serial interconnect technology.

The QuadSMX 3G is a four-channel, bidirectional 2:1 multiplexer/demultiplexer that operates at 3 Gbits/s. It addresses storage- and server-equipment engineers who need a cost-effective gigabit-serial interface for SAS host-controllers for internal or external storage targets, signal repeating, and level shifting. The chip supports both 3- and 1.5-Gbit/s operation and electrically complies with SAS 1.0 or SATA I/II standards.

By incorporating programmable per-port transmit preemphasis and receive equalization with on-chip terminations, the device provides optimal signal integrity and cuts down on external components. There are four levels of preemphasis, three levels of receive equalization, and four output swing levels, all self-adjusting to the application.

The chip demultiplexes the initiator-side receive ports to either the A or B device-side transmit ports (see the figure). In the upstream direction, the chip selects either the A or B device-side receive port to output on the initiator-side transmit ports. The device includes internal out-of-band (OOB) signaling detectors and passes-thru OOB signals. The QuadSMX 3G, made with 0.18-µm CMOS, has an 800-mW power dissipation. It comes in a 11- by 11-mm 100 CABG. Pricing is $14 in 10,000-unit lots.


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