Electronic Design

Chip Solves TCP/IP Bottleneck Problem In High-Speed Ethernet

Ethernet local-area networks have ramped up in speed—significantly. Most run at 1 Gbit/s, and some new systems run at 10 Gbits/s. These high rates are overwhelming computers as more data flows through the networks, leading to bottlenecks with the TCP/IP protocol. The server or PC usually has software that handles TCP/IP, so a hardware solution could be a good idea.

Also known as the Bordeaux, the TN1020 TCP/IP accelerator from Tehuti Networks combines hardware and software. It fits right into the network layer (MAC) between the physical-layer connections and the application drivers. It boosts TCP/IP processing by a factor of 40, relieving the burden on the main processor.

CPU loading is reduced from an average of 80% with an all-software approach to only 35% with the TN1020. An all-hardware TCP/IP offload engine (TOE) would be a bit faster. But these devices are more difficult to design because of interface and driver incompatibilities and links to the operating system.

The TN1020 fits Gigabit Ethernet applications. It can handle a full line rate of 4 Gbits/s and deals with all Internet Protocol (IP) tasks, including IP fragmentation, TCP out of order, and TCP connection establishment. It also can handle up to 65,535 concurrent active connections. Its footprint is one-tenth the footprint of a TOE chip, and it consumes 3 W.

The chip offers full scalability to 10 Gbits/s and standard interfaces. It's fully compatible with Windows, Linux, UNIX, and even proprietary TCP-based operating systems. A network interface card using this chip also is available. A 10-Gigabit chip with similar features will be available this fall.

Tehuti Networks

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