Wide-area network and metro-area network carriers face a critical issue as they roll out their packet-based systems. Even “best effort” services cannot meet the timing requirements of video, gaming, Voice over Internet Protocol, and other services. Typically, expensive GPS receivers and T1/E1 connections step in to achieve the accurate synchronization for quality of service in packet systems.
Or, designers can look to Zarlink Semiconductor’s ZL30301 and ZL30302 Timing over Packet (ToP) chips. These devices use Ethernet switching, circuit emulation, and phase-locked loop technology to reduce timing and synchronization costs while continuing the migration to a truly converged packet network that supports all services.
The ToP technology is built on a hardware-based processing engine combined with control software and clock-recovery algorithms. It encodes and transmits a master clock over existing packet networks and accurately recovers the clock at the client nodes. These chips make it possible to surpass the ITU G.823 and G.824 standards for maximum time interval error (MTIE) and frequency accuracy.
The ZL30301 and ZL30302 encode a primary reference source (PRS) clock at the master node and transmit it over the packet network within a specific packet connection. The client node then recovers the clock through the use of complex algorithms.
For wireless infrastructure applications, the ZL30302 acts as the master. It distributes the PRS clock from the radio network controller (RNC) to Node B over an Ethernet network. The ZL30301 acts as the client at Node B, extracting timing from the packet network and creating an output clock traceable to the PRS. The ZL30301 recovers up to four separate PRS clocks and selects the clock for use within the client node, providing redundancy.
Both chips support differential clock recovery, a mechanism used when the same PRS is available at both the master and client nodes (e.g., as in Sonet). The devices also support adaptive clock recovery, which is commonly used at the edge of the network where a PRS is usually available only at the master node.
The ZL30301 and ZL30302 maintain an average frequency accuracy of less than ±15 ppb with a Statrum 3-quality temperature-compensated crystal oscillator. Some manufacturers use the ITU’s plesiochronous-digital-hierarchy G.823 and G.824 Traffic and Synchronization interface standards as guidelines for packet network timing performance. In the event of a network failure or severe congestion, the chips will put recovered clocks into holdover until the flow of timing packets is restored.
These chips are available now with pricing based on volume.