The-622 Mbps Quad Routing Table (QRT) and 5-Gbps 32 x 32 Quad Switch Element (QSE) chipset is said to virtually eliminate head-of-line blocking via the QSE's sophisticated congestion feedback and Evil Twin Switching algorithm, along with the QRT's per-VC receive queues. The architecture acts as a distributed, output-buffered switch. To manage flows, the QRT can be configured to aggregate similar VCs and support them on their bandwidth and quality-of-service requirements. Congestion management is provided via programmable thresholds on per-VC and per-service class bases. AAL5 support includes Early Packet Discard, CLP-based cell dropping, and EFCI marking. The QSE supports unicast and multicast traffic and its I/O can be grouped for optimal throughput in large switch fabrics. The QRT and QSE have integrated phase aligner circuits for large system development. The devices support backward compatibility with firm's first generation switching chipset.
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